In this role, candidate will be part of the engineering teams implementing DDR, HBM and UCIE PHYs for customer ASICs and SOCs. The project scope includes RTL synthesis, Bump planning , physical design, physical verification, STA and Sign off. Candidate will contribute as a Senior Member of a design team, or as a Project Head working with both internal and external design teams.

Ideal candidate for this role demonstrates excellent technical knowledge, sound communication skills, verbal and written, and awareness of project management issues. Keeps composure during crises and can comfortably handle risks and uncertainty. One has a sound desire to learn and explore new technologies. Demonstrates good investigation and problem-solving skills. Prior knowledge and experience with state-of-the-art CAD tools (ICC2, ICV) and technologies (FinFet) is required. Engineer exercises autonomous judgment in selecting methods and techniques to obtain solutions. Performs in project leadership role. Contributes to complex aspects of a project. Establishes and develops approach to solutions. Provides regular updates to manager on project status. Represents the organization on business unit and/or company-wide projects. Guides more junior peers with aspects of their job. One networks with senior internal and external personnel in own area of expertise

Key Qualification

Typically requires a minimum of 6+ years of related experience

Full knowledge of specialization area plus working knowledge of multiple related areas like DFT, RTL , package design

Ability to Autonomously resolves a wide range of issues in inventive ways on a regular basis.

Prior knowledge and experience with state of the art CAD tools (DC, PT, ICC2, ICV) and technologies (FinFet) is required