Job Description and Requirements

 Should be proven in technical concepts, fundamentals, and good team player. The role involves daily technical interaction with local, US counter parts. This position will be part of SNPS DDR/HBM/UCIe IP implementation team and accountable for the implementation and integration of world class IPs at the cutting-edge technology nodes (14nm,10nm and below). Timing closure above ~2GHz, mixed signal had macro IP integration, Building the efficient clock trees with very tight skew balancing are some of the challenges as part of day-to-day job. Prior working knowledge in the DDR/HBM/UCIe timing closure, implementation would be an added advantage.


This role is for a technical ladder and so it requires hands-on working knowledge preferably with SNPS tools like DC, FC, PT, PT-SI and ICC2. Typically requires 2-4 years of experience after graduation from a reputed university.