THE ROLE:
Synopsys is seeking a Senior Physical Design Engineer and subject matter expert to design and implement processors and sub-systems for our next-generation IPs and processors. The ideal candidate is experienced in the microprocessor development process, resolution of critical problems, and has a consistent track record of delivering timely and high-quality products. Cutting edge experience in Physical Design Methodologies, Flows and tape-out, utilizing the latest process technologies, is preferred. 

KEY RESPONSIBILITIES:

• As a Senior Physical Design engineer, you will contribute to all phases of physical design of high-performance ARC based Processor/Sub-system design from RTL to delivery of our final GDSII.
• Work with RTL/logic designers to drive architectural feasibility studies, explore power-performance-area tradeoffs for physical design closure at the block and Sub System level.
• Drive block physical implementation through synthesis, formal verification, floor planning, bus / pin planning, place and route, power/clock distribution, congestion analysis, timing closure, IR drop analysis, physical verification, ECO and sign-off.
• Work closely across different teams within Synopsys and our customers to deliver quality first pass silicon that meets all performance, power, and area goals.
• Contribute to developing physical design methodologies. Assist in flow development for chip integration.
• Run Physical design verification flow at chip/block level and provide guidelines to fix LVS/DRC violations to other designers.
• Be a highly valued member of our start-up like team through excellent collaboration and teamwork with other physical design engineers as well as with the RTL/Arch. Teams.

 
Preferred experience:

• Breadth and depth of experience in ASIC Physical design, methodology and the latest trends in high-performance microprocessor designs.
• Experience with synthesis, place and route, static timing analysis, noise and power closure.
• Shown Knowledge of HDL languages like Verilog to be able with logic design team for timing fixes.
• Power user of industry standard Physical Design & Synthesis tools.
• 7+ years of experience in integrating IP and ability to specify and drive IP requirements in the physical domain.
• Thorough knowledge of device physics, custom/semi-custom implementation techniques.
• Experience solving physical design challenges across various technologies such as CPU, fabrics etc.
• Experience in extraction of design parameters, QOR metrics, and analyzing trends.
• Experience with DFT & DFM flows.
• Experience in developing and implementing Power-grid and Clock specifications.
• Strong understanding of all aspects of Physical construction, Integration and Physical Verification.
• Deep Understanding of Physical Design Verification methodology to debug LVS/DRC issues at chip/block level.
• Problem-solving and debugging skills.
• Excellent communication and technical documentation skills.
• Ability to provide mentorship, guidance to junior engineers and be a very effective team player.

 
Academic credentials and experience:

• BS/MS in EE/CE
• 7+ years of relevant work experience in ASIC Physical Design from RTL-to-GDSII in FINFET technologies such as 5nm/7nm, 14/16nm.
• Expertise using CAD tools (DC/ICC2, Fusion Compiler, Primetime, Formality, ICV, RedHawk, etc.) for synthesis, formal verification, floor planning, bus / pin planning, place and route, power/clock distribution, congestion analysis, timing closure, IR drop analysis, physical verification, and ECO.
• Scripting experience with Tcl, Perl or Python and ability to drive physical design flow automation.