job description 

Minimum qualifications:

Bachelor's degree in Electrical Engineering or equivalent practical experience.

• 4 years of experience in structural power implementation and checks using power-aware flows.
   
• Experience in UPF power intent, UPF methodology, and downstream usage in DV and Physical Design tools and flows.
   

Preferred qualifications:

• Experience in UPF development of IP, sub-system, or SoC.
   
• Experience with low power design techniques and methodologies.
   
• Experience with scripting languages (e.g., Python, Perl).
   
• Experience in low power static check tools such as VCLP/CLP across RTL to PNR level.
   
• Understanding of SoC Architecture, memory hierarchy, coherency, fabric interconnect protocols, clocking and power management.
   

About the job

Our computational challenges are so big, complex and unique we can't just purchase off-the-shelf hardware, we've got to make it ourselves. Your team designs and builds the hardware, software and networking technologies that power all of Google's services. As a Hardware Engineer, you design and build the systems that are the heart of the world's largest and most powerful computing infrastructure. You develop from the lowest levels of circuit design to large system design and see those systems all the way through to high volume manufacturing. Your work has the potential to shape the machinery that goes into our cutting-edge data centers affecting millions of Google users. 

With your technical expertise, you lead projects in multiple areas of expertise (i.e., engineering domains or systems) within a data center facility, including construction and equipment installation/troubleshooting/debugging with vendors.

Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology.

Responsibilities

• Work with architecture/microarchitecture, architecture/RTL design teams on capturing power intent and convergence.
• Review the front end low power static checks and drive UPF and VCLP convergence and Sign-off.
• Support RTL and DFT teams on the Unified Power Format (UPF) aspect in incorporating Physical Design team feedback.
• Manage cross domains such as DFT, DV and RTL in addressing any UPF/Power intent related methodology and issues.