Job description 

Minimum qualifications:

• Bachelor's degree or equivalent practical experience.
• 5 years of experience in ASIC power management or low power design/methodology.
   
• Experience with ASIC low power flows and power management concepts.
   

Preferred qualifications:

• Master's degree or PhD in Electronics, Computer Engineering, or Computer Science.
   
• Experience with low power architectures and power optimization techniques (e.g., voltage domain design, clock gating, power gating, Dynamic Voltage Frequency Scaling).
   
• Experience with ASIC power modeling and estimation, defining power goals, power management IP and sensors, peak power management/detection/mitigation, in-rush current, adaptive clock distribution, techniques for power/voltage domains design, or competitive power analysis.
   
• Experience in Fabric, MultiMedia, and ISP.