Minimum qualifications:

• Bachelor's degree in Electrical or Electronics Engineering, or equivalent practical experience.
• 7 years of experience in ASIC design implementation and convergence.
• Experience writing production scripts for PnR tools.
   

Preferred qualifications:

• Experience in delivering executive Performance Power Area (PPA) goals across projects.
   
• Experience in CAD flow development.
   
• Knowledge of cutting-edge technology node across foundries.
   
• Knowledge of STA and sign-off convergence methodology.
   
• Knowledge of industry standard implementation tools.
   
• Ability to work with external vendors and drive design improvements.
   

About the job

Our computational challenges are so big, complex and unique we can't just purchase off-the-shelf hardware, we've got to make it ourselves. Your team designs and builds the hardware, software and networking technologies that power all of Google's services. As a Hardware Engineer, you design and build the systems that are the heart of the world's largest and most powerful computing infrastructure. You develop from the lowest levels of circuit design to large system design and see those systems all the way through to high volume manufacturing. Your work has the potential to shape the machinery that goes into our cutting-edge data centers affecting millions of Google users.

With your technical expertise, you lead projects in multiple areas of expertise (i.e., engineering domains or systems) within a data center facility, including construction and equipment installation/troubleshooting/debugging with vendors.

Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology.

Responsibilities

• Develop block implementation flow capable of handling gate designs.
• Work with Design teams to understand requirements and enable scalable solutions.
• Work across functional domains to enable faster sign off convergence during PnR.
• Explore new avenues for Performance, Power, Area improvements to deliver customized solutions for IPs.
• Drive Electronic Design Automation (EDA) vendors to improve their tools to deliver custom solutions for Google.