The Job logo

What

Where

Solutions Engineer

ApplyJoin for More Updates

You must Sign In before continuing to the company website to apply.

Job Description

  • The successful candidate will join a talented Synopsys SLM development team and will have the challenging technical opportunity on various ASIC CAD flow developments and deployments.
  • This a lead position and the candidate will need to be able to lead and manage Synopsys Vietnam Solution team.
  • More than 10+ years of Lead, Develop and support ASIC EDA flow automation and methodology, familiar with ASIC CAD  tools such as Fusion Compiler, Primetime, ICV and etc.
  • Create, release, and maintain standard design scripts to automate EDA tools & flows involves on Synopsys Design tools
  • Experience in physical design and verification with knowledge in blocks to timing,
  • Fluency in scripting languages (TCL, PERC, Python) and ability to develop tools for ASIC automation.
  • Excellent analytical, problem solving and debugging skills with strong interest in semiconductor technology.

Requirements

  • BSEE/CE, or MSEE/PhD with at least 10+ years of industry EDA experience on advanced FINFET nodes
  • Experience in all phases of CAD tools from evaluation, QA, test, release, and user support to documentation
  • Expert in Unix Shell, utilities and scripting language such as Perl/TCL/Python
  • Excellent interpersonal, communication, and presentation skills, along with strong multi-tasking skills, attention to details, and ability to work well in a team & time zone
Set alert for similar jobsSolutions Engineer role in Bengaluru, India
Synopsys Inc Logo

Company

Synopsys Inc

Job Posted

a year ago

Job Type

Full-time

WorkMode

On-site

Experience Level

8-12 years

Category

Software Engineering

Locations

Bengaluru, Karnataka, India

Qualification

Bachelor

Applicants

Be an early applicant

Related Jobs

Synopsys Inc Logo

Staff Technical Program Manager , SLM Solutions

Synopsys Inc

Bengaluru, Karnataka, India

Posted: a year ago

Job Description & Requirements - The Program Management Office (PMO) team oversees the execution, integration, stakeholder engagement, and risk management of change projects executed across the organization. We are seeking an experienced, highly motivated, and high-caliber person to be part of the SLM team with expertise in managing multiple projects. The ideal candidate will understand the strategic direction of the SLM business. The person will perform this pivotal function to ensure timely and successful delivery of the most cutting-edge technologies. The person will manage several hardware development projects from inception to production release, ensuring on-time execution with high quality and meeting development cost targets. In addition, this person coordinates cross-functional dependencies, identifies and escalates issues, manages risk, and measures KPIs. Excellent communication skills are required to influence a wide range of audiences. The job may involve internal and external negotiations, which will majorly impact the area managed and the organization. The candidate will execute against the PMO team’s vision, mission, and goals. Additional Responsibilities Include Manage global engineering projects from concept to customer release Review existing PMO processes and governance and augment, change, or create new processes and governance to ensure team operates predictably and efficiently. Ensure implementation and adherence to PMO processes and governance across the teams. Participate and enable Quality Assurance reviews to monitor adherence. Maintain integrated portfolio project management plan and track interdependencies (inputs, infrastructure, scope, resources, and schedules) to assess impact and communicate it to all stakeholders. Leverage/create tools for “what-if" scenarios. Coordinate weekly, monthly, and ad hoc status reporting across the portfolio. Create dashboards to review status across the portfolio. Drive continuous improvement and adoption of enterprise and change management processes and tools to create efficiency and optimize team’s delivery. Own and manage PMO system of record and knowledge repositories. Job Requirements BS/MS with 10+ years of related experience 10+ years prior PMO or Project Management experience  Integrated Circuit (IC) design engineering experience Exceptional analytical skills with the ability to comprehend, document, evaluate and improve complex project management processes.

Synopsys Inc Logo

Automotive Digital Design Engineer

Synopsys Inc

Bengaluru, Karnataka, India

Posted: a year ago

he Automotive Digital Design Engineer is expected to : Be responsible for specification development, architecture design and RTL development of Automotive specific features / enhancements. Proactively develop safety mechanisms that can be embedded within our IP and reused easily Work closely with the verification team and review verification plan mapping with the specification. Work with product teams to evaluate customer requirements related to quality, functional safety, and automotive reliability. Work closely with the Functional Safety and internal development teams on projects and task planning, progress tracking and reporting. Key Qualifications Must have BSEE in EE with 10+ years of relevant experience or MSEE with 9+ years of relevant experience. Must have proven experience working on Automotive SoC’s / Digital IP’s. Must have proven experience working of one or more of protocols at the IP level: DDR / PCIe / UCIe. Hands on experience with architecting / micro-architecture / detailed design from functional specifications. Hands on experience with Synthesizable Verilog/ System Verilog RTL coding for ASIC designs and Simulation tools. Lint, CDC, synthesis flow and static timing flows, formal checking, etc experience. Working knowledge / experience TCL, Perl, Python is added advantage. Has a solid desire to learn and explore new technologies. Performs in project leadership role & guides more junior peers with aspects of their job. Frequently networks with senior internal and external personnel in own area of expertise. Proficient in English. Formal training in ISO 26262 is preferred. Experience in qualifying systems with embedded hardware to various ISO 26262 ASIL levels up to ASIL D Experience with various ISO 26262 work products such as DFMEA; FMEDA; DFA

Synopsys Inc Logo

Senior Physical Design Engineer

Synopsys Inc

Bengaluru, Karnataka, India

Posted: a year ago

THE ROLE: Synopsys is seeking a Senior Physical Design Engineer and subject matter expert to design and implement processors and sub-systems for our next-generation IPs and processors. The ideal candidate is experienced in the microprocessor development process, resolution of critical problems, and has a consistent track record of delivering timely and high-quality products. Cutting edge experience in Physical Design Methodologies, Flows and tape-out, utilizing the latest process technologies, is preferred.  KEY RESPONSIBILITIES : As a Senior Physical Design engineer, you will contribute to all phases of physical design of high-performance ARC based Processor/Sub-system design from RTL to delivery of our final GDSII. Work with RTL/logic designers to drive architectural feasibility studies, explore power-performance-area tradeoffs for physical design closure at the block and Sub System level. Drive block physical implementation through synthesis, formal verification, floor planning, bus / pin planning, place and route, power/clock distribution, congestion analysis, timing closure, IR drop analysis, physical verification, ECO and sign-off. Work closely across different teams within Synopsys and our customers to deliver quality first pass silicon that meets all performance, power, and area goals. Contribute to developing physical design methodologies. Assist in flow development for chip integration. Run Physical design verification flow at chip/block level and provide guidelines to fix LVS/DRC violations to other designers. Be a highly valued member of our start-up like team through excellent collaboration and teamwork with other physical design engineers as well as with the RTL/Arch. Teams.   Preferred experience : Breadth and depth of experience in ASIC Physical design, methodology and the latest trends in high-performance microprocessor designs. Experience with synthesis, place and route, static timing analysis, noise and power closure. Shown Knowledge of HDL languages like Verilog to be able with logic design team for timing fixes. Power user of industry standard Physical Design & Synthesis tools. 7+ years of experience in integrating IP and ability to specify and drive IP requirements in the physical domain. Thorough knowledge of device physics, custom/semi-custom implementation techniques. Experience solving physical design challenges across various technologies such as CPU, fabrics etc. Experience in extraction of design parameters, QOR metrics, and analyzing trends. Experience with DFT & DFM flows. Experience in developing and implementing Power-grid and Clock specifications. Strong understanding of all aspects of Physical construction, Integration and Physical Verification. Deep Understanding of Physical Design Verification methodology to debug LVS/DRC issues at chip/block level. Problem-solving and debugging skills. Excellent communication and technical documentation skills. Ability to provide mentorship, guidance to junior engineers and be a very effective team player.   Academic credentials and experience: BS/MS in EE/CE 7+ years of relevant work experience in ASIC Physical Design from RTL-to-GDSII in FINFET technologies such as 5nm/7nm, 14/16nm. Expertise using CAD tools (DC/ICC2, Fusion Compiler, Primetime, Formality, ICV, RedHawk, etc.) for synthesis, formal verification, floor planning, bus / pin planning, place and route, power/clock distribution, congestion analysis, timing closure, IR drop analysis, physical verification, and ECO. Scripting experience with Tcl, Perl or Python and ability to drive physical design flow automation.

Synopsys Inc Logo

Staff Application Engineer (AE)

Synopsys Inc

Bengaluru, Karnataka, India

Posted: a year ago

Responsibilities As Staff Application Engineer (AE) , you will be Working on latest Synopsys implementation technologies ( Machine Learning , Physical Synthesis , Multi Source CTS etc ) to solve complex PPA challenges faced by Synopsys customers. Working on benchmarks to displace competition implementation solutions Working with customers to develop and debug RTL-GDS implementation methodologies and flows. Providing technical solutions by identifying the design and/or EDA tool issues and provide appropriate solution for customers Effectively translate the findings into requirements for R&D to improve both tool behavior with enhancements as adaptive long-term solutions. Involved in deployment of new technologies on latest EDA versions and enable customers to migrate to newer versions achieving best PPA Coming up with proactive understanding of customers pain point and come up with innovative solutions to address the same. Closely interacting with Synopsys R&D team and product development team to develop future technologies This role requires you to act as customers advocate while talking to inhouse R&D, and be a product brand ambassador while engaging with customers. Requirements At-least 10 years of experience in Physical Implementation RTL-GDS. Experience in unsupervised debugging and resolving synth & PnR implementation challenges. Candidate must have good exposure towards methodology changes to achieve targeted PPA metrics for complex designs. Proficiency in Synopsys implementation tools is an advantage The person must be self-motivated and dedicated with solid debug skills. Requires proficiency in scripting (tcl / unix / perl). Excellent communication skills including ability to interface with customers and business unit personnel are essential.