Job description 

Job Summary:
We are seeking a Physical Design Specialist for the role of Staff Application Engineer. In this role, you will collaborate with leading-edge customers on advanced nodes (sub-3nm), developing AI-driven RTL-to-GDS methodologies using Synopsys tools like Fusion Compiler and DSO.ai. Your goal will be to achieve the best-in-class PPA with improved cycle time execution. 

Key Responsibilities:
- Partner with leading customers to develop and implement advanced AI-driven RTL-to-GDS methodologies using Synopsys EDA tools, IPs and libraries.
- Create and optimize flows and solutions to meet PPA requirements for high-frequency cores, automotive designs, and high-capacity AI and compute designs.
- Enable the deployment of flows/solution utilizing Synopsys tools like Fusion Compiler, RTL Architect, and AI-based Design Space Optimization engines, along with Tcl/Python scripting.
- Co-publish innovative work and methodologies with partnering customers in international technical conferences.
- Collaborate with the R&D team to share customer requirements and define product specifications for new feature development.
- Demonstrate Synopsys tools and technologies to customers, provide training, and offer technical support.
- Manage customer engagements and technical evaluations, working closely with the account management team.
- Develop new business campaigns and strategies for expanding Synopsys' user segments and verticals.

Key Qualifications:
- Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or in related field.
- 5+ years of experience in ASIC design using Synopsys Implementation or industry-standard tools, with a focus on Placement, Optimization, CTS, and Routing.
- Comprehensive RTL-to-GDSII flow knowledge and hands-on experience with backend P&R tools (e.g., Fusion Compiler/ICC2). Good experience of physical synthesis, timing closure, CTS, macro placement, routing at advanced nodes and timing closure. 
- Strong understanding of advanced node design methodologies and design timing/power constraints.
- Proficient in Tcl/Python scripting.
- Excellent verbal/written communication and presentation skills.
- Familiarity with frontend synthesis tools (Fusion Compiler/Design Compiler), STA (PrimeTime), and physical verification (ICV or similar tools) preferred.