Job description 

Key Requirements:

• Experience: Bachelor’s degree in Electronics with 5+ Years’ or Master’s degree in Electronics with 3+ Years'
• Working experience in Static verification, Design Qualification covering design Lint, Clock/Reset Domain Crossing (CDC/RDC), Low Power (UPF), Design Constraints (SDC) is a MUST
• Exposure to Synopsys EDA tools (SpyGlass, VC SpyGlass, VC LP,VCS, Verdi) would be added advantage
• Solid fundamentals in Digital design, HDLs (Verilog/VHDL) and System Verilog
• Excellent written and oral communication skills is a must as the role requires interfacing with clients, review their challenges, proposing solutions
• Must have working knowledge on UNIX, Tcl and/or any other scripting language to be effective
• Team player, partners with multiple stakeholders, has attention to detail and innovative mindset
• Motivated, doer and self-organized team worker with good social communication skills
• Open to travel, ability to multi-task, be detail-oriented