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Engineer - Physical Design

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Join as an Engineer in physical design, working on SoC physical implementation tasks like floor-planning, placement, routing, and timing analysis. Collaborate with chip level engineers and contribute to timing closure. Must have knowledge of ASIC design flow and tools, timing concepts, and power dissipation. Hands-on experience on physical design flow is essential. Required in Pune, Maharashtra, India, as a full-time on-site opportunity.

Job description 

About the role - you will:

  • Work closely in Design Implementation team for physical design, physical verification & powerrelated activities across various SoCs
  • Be able to work on block level Physical Design implementation using EDA tools
  • Work on Physical design tasks including floor-planning, placement, clock tree synthesis, routing,timing analysis and logical equivalence checking for designs
  • Work on Timing analysis for sign-off corners and modes, report generation, analysis of the reportsand suggesting timing/DRC fixes to fix the violations 
  • Interface with full chip level engineers for full chip timing closure and chip finishing tasks

 

About you:

  • Knowledge of ASIC design flow and tools
  • Good understanding of timing concepts like setup/hold time requirements, calculations ofmaximum frequency of circuit operations, effect of transition and load on circuit performance andpower
  • Should have exposure and working experience with ICC2/PT
  • Basic understanding of power dissipation in different types of circuits
  • Strong analytical, problem solving and debugging skills
  • Good team player with strong verbal and written communication skills
  • Self-motivated and ability to quickly learn new tools and technologies

 

Your experience includes: 

  • ASIC design flow, basic EDA tools for Physical design implementation
  • Place and Route, Timing Analysis, Equivalence check
  • Hands-on experience on physical design flow (floor planning, P&R, CTS, Timing closure)
  • Familiarity and good working knowledge of STA & Constraints is a must
  • Experience in IR (static, dynamic) and EM analysis is highly desirable
  • Technology node: 7nm/ 12nm/ 16nm/ 28nm
  • Strong scripting skills using Tcl, PERL, and Make based flow
Set alert for similar jobsEngineer - Physical Design role in Pune, India
Seagate Technology Logo

Company

Seagate Technology

Job Posted

4 months ago

Job Type

Full-time

WorkMode

On-site

Experience Level

0-2 Years

Category

Technology

Locations

Pune, Maharashtra, India

Qualification

Bachelor or Master

Applicants

Be an early applicant

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