Engineer - Physical Design & Verification

You must Sign In before continuing to the company website to apply.

Smart SummaryPowered by Roshi

Join as an Engineer in Physical Design & Verification at Seagate Technology in Pune, Maharashtra, India. Own complete physical design & verification flow for multiple blocks. Work on power planning, timing closure, signal integrity, and ECO generation. Interface with full chip physical design activities. Ideal candidate has hands-on experience in high-speed digital physical design, scripting skills, and problem-solving ability.

Job description

About the role - you will:

•   Work closely in the Design Implementation team for physical design, physical verification & power related activities across various SoCs
•   Own complete Physical Design & Physical Verification flow for multiple blocks
•   Work on Floor planning, power planning, P&R, CTS, timing closure, IR analysis, and formal equivalence for block level, full chip hierarchical, and flat designs
•   Own parasitic extraction, timing closure, signal integrity, and timing ECO generation/ implementation
•   Work on creating setup and scripts for DRC, LVS, Antenna, and density checks, report generation, analysis, debug, and implementing the fixes in the physical design database
•   Own complete IR/IVD & ESD analysis flow for multiple blocks and chip level
•   Work on Power mesh creation at various IPs (analog, digital Hardmacs, pad-ring) and full chip level
•   Work closely with full chip physical design activities like bumping and RDL routing
•   Interface with full chip level engineers for chip finishing tasks such as LVS, DRC, Antenna check, etc

About you:

•   Self-starter and self-motivated personality
•   Ability to work with ASIC teams and other integration team members
•   Capable of working with general instructions on routine work and detailed instruction on new projects
•   Shares knowledge with others and is keen to build expertise by working collaboratively with team members
•   Ability and willingness to work in a multi-cultural environment and across multiple timezones

Your experience includes:

•   Experience/exposure to high-speed digital physical design and physical verification including ASIC through semi-custom high-speed digital designs from PD through tape out
•   Hands-on experience on physical design / verification flow (floor planning, power planning, P&R, CTS, Timing closure, DRC, LVS). Exposure to EM, IR, low power design with UPF
•   Technology node: 7nm/ 12nm/ 16nm/ 28nm
•   Strong scripting skills using Tcl, PERL, and Make based flow
•   Strong problem solving and debugging skills
•   Good team player with strong verbal and written communication skills

Set alert for similar jobsEngineer - Physical Design & Verification role in Pune, India

Company

Seagate Technology

Job Posted

6 months ago

Job Type

Full-time

WorkMode

On-site

Experience Level

0-2 Years

Related Jobs

Engineer - Physical Design

Seagate Technology

Pune, Maharashtra, India

Posted: 6 months ago

Join as an Engineer in physical design, working on SoC physical implementation tasks like floor-planning, placement, routing, and timing analysis. Collaborate with chip level engineers and contribute to timing closure. Must have knowledge of ASIC design flow and tools, timing concepts, and power dissipation. Hands-on experience on physical design flow is essential. Required in Pune, Maharashtra, India, as a full-time on-site opportunity.

Manager, Physical Design Engineer

Micron Technology

Hyderabad, Telangana, India

Posted: 6 months ago

Manager, Physical Design Engineer role at Micron Technology, Hyderabad, India. Design and develop ASICs for High Bandwidth Memories in AI and high performance computing. Lead design, synthesis, verification, place and route activities. Stay updated with latest design methodologies and mentor junior engineers. Full-time On-site opportunity requiring 12+ years of experience in RTL to GDS flow and proficiency in Verilog or VHDL.

Engineer Product Design - Mechanical Design

Emerson

Pune, Maharashtra, India

Posted: a year ago

Design and develop electrical controls and enclosures for hazardous and heavy industrial applications. Own full product development process from concept to production launch. Collaborate with product management to enhance product features and incorporate innovative technologies. Utilize global lab facilities for product testing. Work on defining and producing new components and materials. Position based in Pune, Maharashtra, India. Full-time, On-site opportunity with Emerson.

Senior Physical Design Engineer

Synopsys Inc

Bengaluru, Karnataka, India

Posted: a year ago

THE ROLE: Synopsys is seeking a Senior Physical Design Engineer and subject matter expert to design and implement processors and sub-systems for our next-generation IPs and processors. The ideal candidate is experienced in the microprocessor development process, resolution of critical problems, and has a consistent track record of delivering timely and high-quality products. Cutting edge experience in Physical Design Methodologies, Flows and tape-out, utilizing the latest process technologies, is preferred.  KEY RESPONSIBILITIES : As a Senior Physical Design engineer, you will contribute to all phases of physical design of high-performance ARC based Processor/Sub-system design from RTL to delivery of our final GDSII. Work with RTL/logic designers to drive architectural feasibility studies, explore power-performance-area tradeoffs for physical design closure at the block and Sub System level. Drive block physical implementation through synthesis, formal verification, floor planning, bus / pin planning, place and route, power/clock distribution, congestion analysis, timing closure, IR drop analysis, physical verification, ECO and sign-off. Work closely across different teams within Synopsys and our customers to deliver quality first pass silicon that meets all performance, power, and area goals. Contribute to developing physical design methodologies. Assist in flow development for chip integration. Run Physical design verification flow at chip/block level and provide guidelines to fix LVS/DRC violations to other designers. Be a highly valued member of our start-up like team through excellent collaboration and teamwork with other physical design engineers as well as with the RTL/Arch. Teams.   Preferred experience : Breadth and depth of experience in ASIC Physical design, methodology and the latest trends in high-performance microprocessor designs. Experience with synthesis, place and route, static timing analysis, noise and power closure. Shown Knowledge of HDL languages like Verilog to be able with logic design team for timing fixes. Power user of industry standard Physical Design & Synthesis tools. 7+ years of experience in integrating IP and ability to specify and drive IP requirements in the physical domain. Thorough knowledge of device physics, custom/semi-custom implementation techniques. Experience solving physical design challenges across various technologies such as CPU, fabrics etc. Experience in extraction of design parameters, QOR metrics, and analyzing trends. Experience with DFT & DFM flows. Experience in developing and implementing Power-grid and Clock specifications. Strong understanding of all aspects of Physical construction, Integration and Physical Verification. Deep Understanding of Physical Design Verification methodology to debug LVS/DRC issues at chip/block level. Problem-solving and debugging skills. Excellent communication and technical documentation skills. Ability to provide mentorship, guidance to junior engineers and be a very effective team player.   Academic credentials and experience: BS/MS in EE/CE 7+ years of relevant work experience in ASIC Physical Design from RTL-to-GDSII in FINFET technologies such as 5nm/7nm, 14/16nm. Expertise using CAD tools (DC/ICC2, Fusion Compiler, Primetime, Formality, ICV, RedHawk, etc.) for synthesis, formal verification, floor planning, bus / pin planning, place and route, power/clock distribution, congestion analysis, timing closure, IR drop analysis, physical verification, and ECO. Scripting experience with Tcl, Perl or Python and ability to drive physical design flow automation.

CPU Physical Design Engineer

Qualcomm

Bangalore Urban, Karnataka, India

Posted: a year ago

Job Area: Engineering Group, Engineering Group > Hardware Engineering   General Summary: As a Physical Design Engineer, you will work with microarchitecture, RTL design and CAD teams to implement the designs meeting aggressive power, area and performance goals using industry standard tools/flows.   Roles and Responsibilities Perform block level implementation using place and route techniques to meet area/timing and power requirements Create floorplan with pin placement, partitions and power grid Generate block level static timing constraints Perform Synthesis, Place & Route on the designs using industry standard tools and deliver GDS Validate the designs for functional and electrical robustness Generate and implement ECOs to fix noise, timing and EM/IR violations Involve in defining correct by construction physical design methodologies.     Minimum Qualifications: • Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience.     Preferred qualifications MS degree in Electrical Engineering; 10 years of practical experience Experience in developing and implementing power grid and clock specifications Experience in all aspects of timing closure for multi-clock domain designs Experience in deep submicron process technology nodes is strongly preferred Knowledge of library cells and optimizations Solid understanding industry standard tools for synthesis, place & route and tapeout flows Solid understanding of physical design verification methods to debug LVS/DRC.  Experience with Synthesis, place and route and signoff  timing/power analysis Knowledge of all aspects of physical construction, integration, physical and electrical verification  Knowledge of basic SoC architecture and HDL languages like Verilog.

Physical Design Manager

Synopsys Inc

Bengaluru, Karnataka, India

Posted: 8 months ago

Physical Design Manager role at Synopsys Inc. in Bengaluru, Karnataka, India, involving leadership in Physical Implementation, RTL to GDSII design, Physical Verification, scripting (Tcl/Unix/Perl), team management, and customer interaction. Full-time On-site opportunity for experienced professionals with structured, organized, and communication skills.