Job description 

What you’ll be doing:

Own micro-architecture and RTL development of design modules.

Micro-architect features to meet performance, power and area requirements.

Work with HW architects to define critical features.

Collaborate with verification teams to verify the correctness of implemented features.

Co-operate with timing, VLSI and Physical design teams to ensure design meets timing, interface requirements and is routable.

What we need to see:

BS / MS or equivalent experience.

2+ years of design experience.

Experience in RTL design of basic design units for at least two or three projects.

Exposure to design and verification tools (VCS or equivalent simulation tools, debug tools like Debussy, GDB).

Good understanding of ASIC design flow including RTL design, verification, logic synthesis, prototyping, DFT, timing analysis, floor-planning, ECO, bring-up & lab debug.

Strong Verilog coding skills.

Ways to stand out from the crowd:

Good debugging and problem solving skills.

Scripting knowledge (Python/Perl/shell).

Good interpersonal skills and ability & desire to work as a part of a team.