This role involves bringing up high speed memory interfaces on complex chips like GPUs and SoCs. You will be responsible for functional validation, IO tuning, and PVT testing of the memory controller and DRAM, paving the way for successful productization of the silicon. Other responsibilities include optimizing Memory IO settings, identifying and resolving functional issues, collaborating with teams, and creating validation test plans. To be considered, you should have a B. Tech or M. Tech in Electronics Engineering or equivalent experience, along with 5+ years of experience in the semiconductor industry and strong understanding of DRAM types like GDDR/LPDDR.
