What you’ll be doing:

• Bring up high speed memory interface on complex chips like GPUs and SoCs.
• Functional validation, IO tuning and PVT testing of the memory controller and DRAM paving the way for successful productization of the silicon.
• Optimizing Memory IO settings to support multiple memory configurations involving different types of DRAMs and vendors.
• Identify any functional issues and perform root-cause analysis and drive closure of the issues found. Coordinate with design, arch, and board teams, where required.
• Collaborate with pre-Si team to understand the new features and create appropriate validation test plans.

What we need to see:

• B. Tech or M. Tech in Electronics Engineering or equivalent experience
• 5+ years of experience in the semiconductor industry with a minimum of 2 years in memory interface validation.
• Strong understanding of the protocol for DRAM types like GDDR/LPDDR
• Familiarity with HW lab environment and understanding of lab equipment like DMM, Oscilloscope, thermal solutions etc.
• Background in understanding PCB stack-up, board layouts, power planes, SI guidelines.
• Experience in writing lab automation scripts using C/Python/Perl.
• A strong standout colleague; self-motivated with great interpersonal skills