ASIC Digital Design Engr, Sr I
We are looking for a Senior ASIC Digital Verification Engineer to join our team in Delhi/Bangalore, India. You will be responsible for developing functional verification solutions for interface IP solutions. The role requires expertise in UVM, System Verilog, and programming languages such as TCL Perl or Python. If you are passionate about delivering digital IP to the semiconductor industry, join us!
Job Description and Requirements
We’re looking for a Senior ASIC Digital Verification Engineer to join the team.
Based in our offices in Delhi/Bangalore India, you will be a senior member of the Synopsys Solutions Group team, which is developing interface IP solutions for PCIe & CXL.
The role is hybrid with an expectation of working from the office 3 days per week.
You will responsible for the development of functional verification solutions for the IP which is used in end-customer applications such as server farms, AI/machine learning, automotive, etc. You will work with our internationally-based team of architects/designers/other verification team members to specify requirements and follow through on the implementation. Interested in such a role?
This is a key position within the team in India, which is delivering digital IP to the semiconductor industry.
You will:
- Write verification plans and specifications
- Make architecture decisions on test bench design
- Implement test bench infrastructure and write test cases
- Implement a coverage driven methodology
- Perform a technical lead role
Key Qualifications
- 5+ years' relevant experience.
- Proficient in UVM
- Object oriented coding and verification solutions for productivity, performance, and throughput
- Experience of techniques such as assertion verification, coverage analysis and System Verilog for protocol-oriented performance analysis and debug
- Programming skills such as System Verilog, TCL Perl or Python
- The ability to work independently, precisely and to drive innovation
- Good communication skills.