Job Description

Determines, specifies and evaluates the viability of complex hardware features and structures and ensures that software and hardware designs interface correctly. Designs framework for particular functions. Defines, documents and tests processes for inclusion into technical platforms, subsystem specifications, input/output and working parameters for hardware and/or software compatibility. Identifies, analyzes and resolves subsystem and/or SoC design weaknesses. Influences the shaping of future products by significantly contributing to the architecture used across design families. Provides multilayered technical expertise for next generation initiatives. The PCIe Solution Architect will be responsible for Intel FPGA 5G/Wireless IP interface/solution architecture and will provide technical leadership to the rest of the team in these domains. The architect will be responsible for working with the peer architects to define the overall solution. The architect will require a broad knowledge in 5G / Wireless solutions, specifications and use cases to make trade-off analysis between Hard-IP or Soft-IP or Hybrid as a better solution option. Protocol IP design knowledge, and the ability to comprehend global data movements in the context of an FPGA is a plus.

Qualifications

The 5G Wireless Solution IP Architect will be responsible for architecting Intel FPGA based 5G Wireless solutions. 5G solution focuses on provides faster connectivity speeds, ultra-low latency and greater bandwidth is advancing societies, transforming industries and dramatically enhancing day-to-day experiences. Services that we used to see as futuristic, such as e-health, connected vehicles and traffic systems and advanced mobile cloud gaming have arrived. With 5G technology, we are helping to create a smarter, safer and more sustainable future The candidate is responsible for defining the overall architecture and execution of IP architecture that enables a competitive end to end solution for that IP. This includes defining the right feature set, right architecture considering both HW/SW interactions that meets the feature requirements including power and performance. The candidate will work closely with IP Planning, Business Divisions, Post Silicon Validation team, Hardware Engineering team, customers and CTO Office to define the future of FPGA IP architectures to realize the objectives. 

The successful candidate's minimum qualifications will include the following: 

� BS in Electrical Engineering or equivalent 

� Deep understanding of Hardware Design, with a minimum of 10 years of experience in design and architecture 

� Experience in 5G and wireless communications protocols 

� Good understanding of IP protocol stacks over wireless links and RF performance metrics 

� Experienced with high bandwidth, low latency communication and processing 

� Strong desire to go deep on system level issues and drive problems to closure in a team-based environment with a proactive demeanor, while able to work under own initiative.