We are seeking a qualified candidate to join our team as an IP Verification Engineer. In this role, you will be responsible for designing and implementing verification environments for complex IP such as Ethernet, CXL, and Storage. You will develop UVM-SV scoreboards for self-checking regressions and functional coverage to ensure thorough testing. Additionally, you will create and manage verification plans using Cadence vManager tools and participate in technical review meetings. The ideal candidate will have a degree in Electrical/Electronic Engineering or a related discipline and at least 4 years of experience in the microelectronics/EDA industry. Experience with Verilog RTL Design and Metric Driven Verification is essential. Strong communication and planning skills are required, and fluency in written and spoken English is necessary. Experience with front-end design tools, such as LINT, Synthesis, and CDC analysis is preferred. Knowledge of quality processes, including ISO-9001 and ISO-26262, is also a plus.
