Job Description

• Responsible for understanding micro architectural details of designs, preparing test plans and developing re-usable test bench components
• Executing test plans and reporting bugs to drive the development of flawless designs
• Responsible for executing RTL verification as well as GLS activities
• Strong hands-ON technical contributions and ability to mentor junior team members
• Will be actively involved in identifying and addressing verification pain points and creatively improving the end-to-end verification methodologies

Qualifications
 

Required Skills :

• Test bench architecture and bus functional models development
• Proficient in coding Pre-Silicon functional validation tests to verify design to meet spec. requirements
• Creates efficient test plans for RTL validation and Gate level simulations
• Expertise in verification of design blocks (IP) and Subsystems for SoC(s)
• Expertise in SoC level validation
• Expertise in System verilog , UVM, and/or OVM based verification methodologies
• Experience in OOPs concepts, coverage driven constrained random validation
• Good knowledge on AMBA standards (OCP, AXI, AHB, APB)
• Working knowledge of scripting, SVA
• Looking for highly motivated individuals and ability to deal with ambiguity
• Ability to work with external stakeholders for different verification components/test development

Must to have skill set :

• Passion to work on new designs and drive best Verification practices
• Good to have skill set :
• Good knowledge and working experience on LPDDR protocols
• Good knowledge and working experience on PCIe or CXL high speed protocols

Qualifications
Masters degree with 7+ years of relevant industry experience or a Bachelor degree with 9+ years of relevant industry experience