Job Summary

 This position requires the development of Verification IPs for various standards specifications.

● Developing performance optimized VIPs for latest (draft/ballot) specifications of various protocols and interfaces.
● Verifying the VIPs for proper functionality and system scenarios (including erroneous conditions)
● Developing test suite and compliance test suite for 100% functional coverage for a given specification.
● Documenting the design and implementation for engineering details and for customers.
● Interacting with internal and external customers and resolving issues in a timely manner.

Job Responsibilities

• Good working knowledge of various verification concepts such as Verification architecture, coverage, checkers, test plan etc.
• Knowledge of Verification environments based on UVM, System Verilog
• Should have participated in building IP/full chip verification environments, verification planning and closure process.
• Domain expertise in MIPI, AMBA, NVMe, PCIe, would be a strong plus
• Programming skills: C, Verilog, System Verilog mandatory. C++ would be a strong plus.
• Very good debugging and analytical skills
• Should have good communication skills and should be a good team player

Qualifications

• BE/BTech/ME/MS/MTech in Electrical/Electronics

Experience and Technical Skills required

5+ years of experience in Verification

• Expertise in one or more domains – UVM, System Verilog

Behavioral skills required

• Must possess strong written, verbal and presentation skills
• Ability to establish a close working relationship with both customer peers and management
• Explore what’s possible to get the job done, including creative use of unconventional solutions
• Work effectively across functions and geographies
• Push to raise the bar while always operating with integrity