Job Summary:

Drives development of products and technologies and has material responsibility for the success of that product/technology.

Job responsibilities

• Architect, develop, champion, and implement metric-driven mixed-signal verification solutions, in the areas of:
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  • Digital/DMS/AMS testbench creation and generation
  • Automatic Model generation and testing
  • Cadence Design Systems AMS simulation flows
  • Mixed-Signal Assertions and Checkers
  • Behavioral Modeling and Model Validation Methodologies
  • Mixed-Signal VIP integration and testing
  • Mixed-Signal emulation flows and practices

• Power intent verification including Low power states, state retention and CPF/UPF integration
• Push technology for mixed-signal modeling, simulation and DV in order to improve mixed signal verification efficiency and accuracy.
• Ensure scalable mixed-signal DV solutions to cover the breadth of IPG offerings including SerDes, DDR, A2D converters and custom solutions
• Drive adoption of analog behavioral modeling methodologies for efficient mixed-signal verification
• Develop efficient debug solutions and techniques
• Develop efficient and accurate full stack mixed signal methodology for entire IP stack from controller to analog circuit.
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• Mentor junior engineers Collaborate closely with
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  • Digital, Analog, Firmware and Test engineers 
  • Internal methodology and tool development teams, such as, Virtuoso/ADE/Xcelium. PDK teams and
  • Customer management and engineering support teams

Experience and Technical Skills required

• 5-12 Years’ experience in working with Digital and Analog mixed-signal environment and teams.
• Must have good written and verbal cross-functional communication skills.
• Proven experience in most of the following:
• Creating Verification infrastructure (test-bench, environment, scripting)
• Scripting of verification flows, design automation
• Debugging verification testcases
• Knowledge of existing and upcoming standards such as PCIE, USB, DDR4 etc.
• Must be comfortable interacting across the IPG development team including the ability to understand design constraints.
• Knowledge of Mixed-Signal Cadence tools and mixed signal methodology is a plus
• Knowledge of SystemVerilog and UVM Test environment and methods is a plus
• Working knowledge of revision control tools such as SOS, SVN is a plus

Education Level: Bachelor's Degree (MSEE Preferred)