This position requires a highly motivated and experienced engineer to work with Synopsys’ customers on integrating leading edge Interface IP (IIP) into their ASIC SoC/systems for next generation products utilizing our DDR/LPDDR4/4x/5. The position offers opportunities to work on Synopsys IIP and the latest industry specifications/applications on various hot market segments. The position will provide IIP integration guidance to customers throughout their SoC flow to resolve technical challenges, perform integration reviews at key milestones and support silicon/system bring-up. Some travel may be required.

Key Qualifications

• This position typically requires 5 to 7 years of related design or customer experience, but we may also consider candidates with less experience with the right academic background.
• ASIC design experience with Simulation/Verification and RTL Synthesis.
• Experience in one or multiple steps on IP design or integration flow of ASIC / SoC design (such as simulation/verification, RTL synthesis, floor planning, physical design, timing closure, etc.) or silicon bring-up/characterization in a system environment.

Preferred Experience

• Technical knowledge with any Interface IP such as PCIe, USB, MIPI, HBM DDR, LPDDR Protocols, Specification, Design, Verification, and Implementation.
• Excellent organization skills, communication skills and ability to interact with customers
• Proven track record in meeting tight schedules and handling multiple projects concurrently