Job description 

General Summary:

• As a Physical Design Engineer, you will work with microarchitecture, RTL design and CAD teams to implement the designs meeting aggressive power, area and performance goals using industry standard tools/flows.

Roles and Responsibilities

• Perform block level implementation using place and route techniques to meet area/timing and power requirements
• Create floorplan with pin placement, partitions and power grid
• Generate block level static timing constraints
• Perform Synthesis, Place & Route on the designs using industry standard tools and deliver GDS
• Validate the designs for functional and electrical robustness
• Generate and implement ECOs to fix noise, timing and EM/IR violations
• Involve in defining correct by construction physical design methodologies.

Minimum Qualifications:

• Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience. 
OR
Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. 
OR
PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience.

Preferred qualifications

• MS degree in Electrical Engineering; 5 to 15 years of practical experience
• Experience in developing and implementing power grid and clock specifications
• Experience in all aspects of timing closure for multi-clock domain designs
• Experience in deep submicron process technology nodes is strongly preferred
• Knowledge of library cells and optimizations
• Solid understanding industry standard tools for synthesis, place & route and tapeout flows
• Solid understanding of physical design verification methods to debug LVS/DRC. 
• Experience with Synthesis, place and route and signoff  timing/power analysis
• Knowledge of all aspects of physical construction, integration, physical and electrical verification 
• Knowledge of basic SoC architecture and HDL languages like Verilog.