Job Location: Hyderabad, Telangana
Role and Responsibilities

• Responsible for Layout design and development of critical analog, memory, and custom digital block.
• Perform layout verification like LVS/DRC/Antenna, quality check and documentation.
• Responsible for on-time delivery of block-level layouts with acceptable quality.
• Demonstrate leadership Skill in planning, area/time estimation, scheduling, delegation, and execution to meet project schedule/milestones in multiple project environment.
• Guide junior team-members in their execution of Sub block-level layouts & review their work.
• Contribute to effective project-management.
• Effectively communicating with Global engineering teams to assure the success of layout project.

Qualification/Requirement:

• 3 to 6-year experience in analog/custom layout design in advanced CMOS process.
• Expertise in Cadence VLE/VXL and Mentor Graphic Calibre DRC/LVS is a must.
• Should have hands on experience in creating layout of critical blocks such as Temperature sensor, PLL, ADC, DAC, LDO, Bandgap, Ref Generators, Charge Pump, Current Mirrors, Comparator, Differential Amplifier etc.,
• Good understanding of Analog Layout fundamentals (e.g., Matching, Electro-migration, Latch-up, coupling, crosstalk, IR-drop, active and passive parasitic devices etc.)
• Understanding layout effects on the circuit such as speed, capacitance, power and area etc.,
• Ability to understand design constraints and implement high-quality layouts.
• Excellent command and problem-solving skills in physical verification of custom layout.
• Multiple Tape out support experience will be an added advantage.
• Excellent verbal and written communication skills.

Education:
BE or MTech in Electronic/VLSI Engineering