RTL Design Engineer, Silicon, Google Cloud
Google
Bengaluru, Karnataka, India
Minimum qualifications: Bachelor's degree in Electrical Engineering or equivalent practical experience. 8 years of experience in ASIC development with Verilog/SystemVerilog, Vhsic Hardware Description Language (VHDL), or Chisel. Experience with ASIC design verification, synthesis, timing/power analysis, and Design for Testing (DFT). Experience in SoC cycles. Preferred qualifications: Experience with scripting languages (e.g., Python or Perl). Knowledge of arithmetic units, bus architectures, processor design, accelerators, or memory hierarchies. Knowledge of high performance and low power design techniques. Knowledge of Field Programmable Gate Array (FPGA), emulation platforms, and SoC architecture. Knowledge of assertion-based formal verification. About the job Our computational challenges are so big, complex and unique we can't just purchase off-the-shelf hardware, we've got to make it ourselves. Your team designs and builds the hardware, software and networking technologies that power all of Google's services. As a Hardware Engineer, you design and build the systems that are the heart of the world's largest and most powerful computing infrastructure. You develop from the lowest levels of circuit design to large system design and see those systems all the way through to high volume manufacturing. Your work has the potential to shape the machinery that goes into our cutting-edge data centers affecting millions of Google users. In this role, you will collaborate closely with Design and Verification Engineers in active projects, creating architecture definitions with Register-Transfer Level (RTL) coding, and running block level simulations. You will also be working with the Silicon Validation team, defining the bring-up plan for an IP and assisting them during the bring-up activity. You will contribute in all phases of complex Application-Specific Integrated Circuit (ASIC) designs from design specification to production. You will collaborate with members of architecture, software, verification, power, timing, synthesis to specify and deliver high-quality System on a Chip (SoC)/RTL. You will solve technical problems with innovative micro-architecture, practical logic solutions, and evaluate design options. Behind everything our users see online is the architecture built by the Technical Infrastructure team to keep it running. From developing and maintaining our data centers to building the next generation of Google platforms, we make Google's product portfolio possible. We're proud to be our engineers' engineers and love voiding warranties by taking things apart so we can rebuild them. We keep our networks up and running, ensuring our users have the best and fastest experience possible. Responsibilities Manage the block level design documents such as interface protocol, block diagram, transaction flow, pipeline. Perform RTL development (e.g., coding and debug in Verilog, SystemVerilog, function/performance simulation debug. Participate in synthesis, timing/power closure, and FPGA/silicon bring-up. Participate in test plan and coverage analysis of the block and SoC-level verification. Work closely with the Silicon Validation team on any functional, power and performance debugs. Communicate and work with multi-disciplined and multi-site teams.
