Formal Verification Engineer at Synopsys, you will be responsible for formally verifying complex design IPs. Synopsys IP Group has a strong formal verification methodology that enables hardware verification engineers to use FV tools and techniques successfully on complex and/or critical RTL logic. The job involves very close interaction with the designers, architects, verification engineers and Synopsys's Tool Development Group to drive verification projects.

Expectations from the candidate

1. Help decide on the best applications of formal verification techniques to various parts of the design.

2. Review functional and micro-architectural specifications, define the scope for formal verification, and create high-quality formal verification testplans to sign-off on the corresponding design implementation.

3. Build formal verification testbenches, code assertions and constraints, and apply abstraction techniques to converge the targeted properties or to achieve reasonable proof-depth.

4. Apply formal coverage techniques for analysing over-constraints and for measuring functional coverage.

Required skills

1. Pursuing or completed BTech/ MTech degree

2. Good understanding of hardware micro-architecture and design

3. Proficiency in HDLs like Verilog, SystemVerilog

4. Familiarity with SystemVerilog Assertions (SVA) and basic concepts of formal property verification

5. Good debugging and problem-solving skills

6. Scripting knowledge (Python/Perl/shell)

7. Good interpersonal and communication skills and dream to work as a great team member

Good to have skills

1. Academic projects related to formal verification or digital design verification

2. Exposure to formal verification tools like VCFormal, Jasper, Yosys etc

3. Knowledge of protocols like AXI, CHI, PCIe, DDR, etc