Job Description and Requirements

Seeking a motivated and innovative digital verification engineer with excellent theoretical and practical background in high-speed data recovery circuits. Candidate will be involved in verifying current and next generation SERDES products.

Responsibilities:

• Writing constrained-random System Verilog test benches using UVM and VMM.
• Writing new cover group and examine functional, assertions and code coverage.
• Defining and tracking verification test plans;
• Debugging RTL and gate-level simulations failures;
Candidates should have experience writing scripts in languages such as Perl, Python, Unix shell. 

Requirements:

Bachelor’s or Masters Degree in ECE/EEE