The Job logo

What

Where

MTS Silicon Design Engineer ( DFX RTL verification Enigneer

ApplyJoin for More Updates

You must Sign In before continuing to the company website to apply.

Smart SummaryPowered by Roshi
Seeking MTS Silicon Design Engineer to drive DFT feature verification for next-gen Graphics processors. Responsibilities include defining DFT feature verification requirements, developing test plans, and constructing validation infrastructure for Graphics products. Preferred experience includes 8+ years in ASIC/Custom design, proficiency in using UVM testbenches, Verilog, System Verilog, C, C++, and EDA simulation tools.

Job description 

THE ROLE: 

Our Graphics DFT team is looking for an experienced design verification professional to drive DFT feature verification for our next generation Graphics processors.

The focus of this role is to plan, build, and execute the verification of new and existing features for AMD’s graphics processor IP, resulting in no bugs in the final design.   

  

THE PERSON:  

You have a passion for modern, complex processor architecture, digital design, and verification in general. You are a team player who has excellent communication skills and experience collaborating with other engineers located in different sites/timezones. You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems. 

  

KEY RESPONSIBILITIES:  

  • Define and develop DFT feature verification requirements and test plans for current and next generation Graphics products
  • Build comprehensive validation infrastructure including test bench components, agents, monitors, checkers, scoreboards
  • Construct SystemVerilog and/or C/C++ models and test sequences for comprehensive feature simulation, evaluate feature coverage and regression health
  • Develop pre-silicon validation vectors and coverage bins to ensure feature verification completeness and support post silicon bring-up
  • Participate in methodology development to increase verification efficiency and effectiveness.

  

PREFERRED EXPERIENCE:  

  • 8+ years of ASIC/Custom design and testability experience
  • Proficient in IP level ASIC verification 
  • Proficient in debugging firmware and RTL code using simulation tools  
  • Proficient in using UVM testbenches and working in Linux and Windows environments 
  • Experienced with Verilog, System Verilog, C, and C++   
  • Experience with EDA simulation tools including Synopsys VCS, Cadence NCSIM, Verdi
  • Experience working with UVM, OVM or equivalent
  • Experience with formal verification techniques and industry tools
  • Experience with scripting languages including Tcl/Perl/Ruby/Python
  • Working knowledge of Unix/Linux OS and debug tools
  • Strong analytical skills and attention to detail
  • Excellent written and verbal communication
  • Strong interpersonal skills and proven leadership

  

ACADEMIC CREDENTIALS:  

  • Bachelors or Masters degree in computer engineering/Electrical Engineering 

 

 

#LI-SR4

Set alert for similar jobsMTS Silicon Design Engineer ( DFX RTL verification Enigneer role in Bengaluru, India
AMD Logo

Company

AMD

Job Posted

9 months ago

Job Type

Full-time

WorkMode

On-site

Experience Level

8-12 Years

Category

Software Engineering

Locations

Bengaluru, Karnataka, India

Qualification

Bachelor or Master

Applicants

Be an early applicant

Related Jobs

AMD Logo

MTS Silicon Design Engineer

AMD

Bengaluru, Karnataka, India

Posted: a year ago

THE ROLE: The position will involve working with a very experienced physical design team of CPU core and is responsible for delivering the physical design of tiles to meet challenging goals for frequency, power and other design requirements for AMD next generation processors in a fast-paced environment on cutting edge technology.   THE PERSON: Engineer with good attitude who seeks new challenges and has good analytical and communication skills. Candidate needs to have the ability and desire to learn quickly and should be a good team player.   KEY RESPONSIBILITIES:  Implementing RTL to GDS2 flow Handling Floor-plan, Physical Implementation of Power-plan, Synthesis, Placement, CTS, Timing Closure, Routing, Extraction, Physical Verification (DRC & LVS), Crosstalk Analysis, EM/IR, Formal Equivalence Handling different PNR tools - Synopsys Fusion Compiler, ICC2, Design Compiler, PrimeTime, StarRC, Mentor Graphics Calibre, Apache Redhawk, Cadence Genus, Innovus.   PREFERRED EXPERIENCE: 12+ years of professional experience in physical design, preferably with high performance designs. Experience in automated synthesis and timing driven place and route of RTL blocks for high speed datapath and control logic applications. Experience in automated design flows for clock tree synthesis, clock and power gating techniques, scan stitching, design optimization for improved timing/power/area, and design cycle time reduction. Experience in floorplanning, establishing design methodology, IP integration, checks for logic equivalence, physical/timing/electrical quality, and final signoff for large IP delivery Strong experience with tools for logic synthesis, place and route, timing analysis, and design checks for physical and electrical quality, familiarity with tools for schematics, layout, and circuit/logic simulation Versatility with scripts to automate design flow. Strong communication skills, ability to multi-task across projects, and work with geographically spread out teams Experience in FinFET & Dual Patterning nodes such as 16/14/10/7/5nm Excellent physical design and timing background. Good understanding of computer organization/architecture is preferred. Strong analytical/problem solving skills and pronounced attention to details.   ACADEMIC CREDENTIALS: Qualification: Bachelors or Masters in Electronics/Electrical Engineering

AMD Logo

MTS Silicon Design Engineer ( RTL Design ) – Artificial Intelligence Group

AMD

Hyderabad, Telangana, India

Posted: a year ago

THE ROLE:   The focus of this role is to plan, build, and execute the design and integration of new and existing features for AMD’s AI Engine IP to improve AMD's abilities to deliver the highest quality, industry-leading technologies to the market. The AI Group furthers and encourages continuous technical innovation to showcase successes as well as facilitate continuous career development.       THE PERSON:    You have a passion for modern, complex processor architecture, digital design, SOC design and design automation in general. You are a team player who has excellent communication skills and experience collaborating with other engineers located in different sites/timezones. You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems.     KEY RESPONSIBILITIES:    Collaborate with architects, Verification engineers, and Physical design Engineers to understand the new features to be designed and integrated in SoC.  Identify areas for automation and create solutions to improve productivity and quality and continuously improve the automation process by exploring new tools and technologies. Integrate various design tools and flows to create a cohesive design environment. Participate in design reviews and provide feedback on other team members' designs. Provide technical support to other teams.  Debug test failures to determine the root cause; work on RTL design to resolve design defects.        PREFERRED EXPERIENCE:    Proficient in Verilog and System Verilog with good understanding of RTL design flows and process Using the tools in ASIC development such as Lint, CDC, Design Compiler and Primetime Experience with version control system such as perforce Good with Scripting languages such as Python, Perl, Makefile, TCL and unix shell Automating workflows in a distributed compute environment. Familiarity with standard protocols such as AXI Stream and AXI MM.  Familiarity in using UVM testbenches for debugging RTL code using simulation tools   Proactive, creative curious and motivated    ACADEMIC CREDENTIALS:    Bachelors or Masters degree in computer engineering/Electrical Engineering 

AMD Logo

RTL Design

AMD

Bengaluru, Karnataka, India

Posted: a year ago

WHAT YOU DO AT AMD CHANGES EVERYTHING We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences – the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world’s most important challenges. We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives.  AMD together we advance_   PMTS SILICON DESIGN ENGINEER   THE ROLE:   As a member of the Infinity Fabric Architecture and RTL team, you will help build the next generation scalable coherent interconnect to provide connectivity between CPU, GPU and special purpose accelerators. Every product that AMD sells has its own custom-designed Infinity Data Fabric, so this role gives an engineer the opportunity to work on a broad array of products that address a variety of markets, including traditional servers, high performance computing, client desktop and laptop PCs, machine intelligence, graphics, console gaming, embedded, and customer-specific applications. It is a challenging position that involves working at a fast pace of innovation on the cutting edge of technology. Come join the AMD team!    THE PERSON:    You have a passion for modern, complex processor architecture, digital design as well as verification/design quality. You are a team player who has excellent communication skills, strong analytical & problem-solving skills and are willing to learn and ready to take on problems. A global mindset and ability to work in a multi – site environment are keys to being successful in this role.    KEY RESPONSIBLITIES: Early architectural/performance exploration through micro-architectural definition and design Optimize the design to meet power, performance, area and timing requirements Write easily readable and synthesizable Verilog RTL Run some unit level testing to deliver quality code to the Design Verification Team Create assertions to improve coverage and cover points to analyze coverage of the design Create well written block level design documentation Participate in post silicon functional and performance debug and tuning Mentor junior engineers PREFERRED EXPERIENCE: Proven experience designing logic blocks in CPU, GPU, NOC, or cache designs Strong understanding of digital electronics and high-speed designs(>1GHz)   Strong understanding of multi-processor coherency, memory ordering, i/o ordering, interrupts, MMU and caches   Excellent knowledge of Verilog and System Verilog   Good debugging and analytical skills   Exposure to Design for Test, understanding of scan concepts and writing DFT friendly RTL   Working knowledge of C, C++ and a scripting language like Perl or Python   Working knowledge of x86 or ARM ISA is a plus

AMD Logo

Sr. Manager Silicon Design Engineering ( Verification )

AMD

Hyderabad, Telangana, India

+1 more

Posted: a year ago

THE ROLE: The focus of this role in the AECG ASIC organization is to lead verification and emulation for next generation ASICs that meet Engineering, Business and Customer requirements.     THE PERSON: You have a passion to lead high performance ASIC verification and emulation teams. You are a team player who has excellent communication skills and experience collaborating in a corporate environment with other architects & engineers located in different sites/time-zones. You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems.   KEY RESPONSIBILITIES:  Verifying RTL implementation for complex digital blocks and ASIC top level to ensure high quality Develop verification strategies for new features, plan volume validation and coverage strategies Writing testplan, developing testbenches, coding test/sequences and checker to support IP level verification in constrained-random and/or directed verification environments using System Verilog & UVM Drive coverage analysis and take necessary actions to meet coverage goals Integrate VIPs as needed Closely work with design teams to drive feature enablement Lead internal and external teams   PREFERRED EXPERIENCE:   Strong foundation in SoC architecture and processor systems with proven years of experience  Good analytical problem solving, and attention to details Working knowledge of C, SystemC, and Python Excellent written and verbal communication skills Knowledge of CPU, AXI Interconnect, and I/O peripherals Knowledge of SOC development flow and accelerator IP Experience in micro-architecture and digital design/verification Knowledge of power management, boot, security and RAS architectures Exposure to performance modeling and analysis Expert experience with implementation of UVM/OVM and/or Verilog, System Verilog test benches and/or BFMs is required Working experience in full chip emulation using industry standard emulators from Synopsys, Cadence and Mentor. Knowledge of bus protocols like AXI/AHB Knowledge of protocols like PCIe, Ethernet and/or NVMe preferred Strong understanding of simulation tools and knowledge of scripting languages like Perl, tcl or cshell Highly motivated, Self-starter individual with ability to work in a fast-paced team environment    EDUCATION & EXPERIENCE:  BS, MS or PhD degree in in Electrical Engineering or Computer Science. 10years of experience in an ASIC architect role leading to an understanding of end-end development.    LOCATION: Bangalore (preferred) Hyderabad