Job description
What will you do at Ciena?
This position is for an experienced FPGA verification engineer for supporting FPGA development Programs for Packet Networking hardware acceleration of Ethernet, MPLS, and IP OAM and SAT (Service Activation Testing) protocols, statistics, packet timing, TDM circuit emulation, as well as, system glue logic for packet access switching and routing platforms.
The successful candidate will lead the chip level verification activities for a variety of FPGA designs and will be responsible for (but not limited to) the following:
- establish verification methodology, architecture, and infrastructure including models, generators, monitors, scoreboards, etc.
- work with the design team to establish test priorities and coverage targets.
- create verification plans
- create and executing testcases
- triage regressions, providing reports to the team and driving bug fix activities
- collaborate with peers and mentor junior verification engineers on verification methodologies and best practices
- provide accurate and timely project schedule estimates
Responsibilities
- experience in developing testbench environments using System Verilog and UVM
- experience with both directed and constrained-random stimulus generation
- good problem solving and debugging skills
- a good sense of overall priorities and ability to make smart trade-offs given the typical timelines of FPGA designs
- experience with Mentor Graphics Questa and Synopsys VCS verification tools
- working knowledge of PC and Unix/Linux operating systems
General Activities
• Capability to give technical leadership to small team of Verification engineers (mentorship)
• Independent self-starter
• Strong commitment to product excellence
• Excellent communications skills
Collaboration with stakeholders
Areas of impact
Experience
- Bachelor's degree in Engineering or equivalent
- Minimum 5+ Years Experience as an FPGA/ASIC Verification Engineer.