Job description 

Qualifications

Qualifications

•  
  • 7 or more years of experience in design verification with a proven track record of delivering complex CPU or SoC IP’s
  • 2 or more years of experience with ATE/ATM vector generation and vector verification for Post Si Production Testing
  • Experience with JTAG/TAP debug interfaces
  • In depth knowledge of verification principles, testbenches, stimulus generation, and UVM or C++ based test environments.
  • Substantial background in debugging RTL (Verilog) designs as well as simulation and/or emulation environments
  • Scripting language such as Python or Perl or Tcl/Tk
  • Experience of delivering complex System level Tests (SLT) to PE team
  • knowledge in high-speed protocols like DDR, PCIe, Ethernet 
  • Processor based testbenches and emulation

Ability to meet Microsoft, customer and/or government security screening requirements are required for this role. These requirements include but are not limited to the following specialized security screenings: Microsoft Cloud Background Check: This position will be required to pass the Microsoft Cloud Background Check upon hire/transfer and every two years thereafter.

Responsibilities

Responsibilities

The AISoC silicon team is seeking a passionate, driven, and intellectually curious computer/electrical engineer to deliver premium-quality designs once considered impossible. We are responsible for delivering cutting-edge, custom IP and SoC designs that can perform complex and high-performance functions in an extremely efficient manner.

• Plan the SoC level verification of IP/Subsystem interacting with design engineers to identify verification test scenarios.
• Familiar with the constrained-random verification environments using SystemVerilog and UVM, and able to enhance & develop the verification component of the testbench.
• Execute the IP/Subsystem SoC level verification plan
• Analyse and debug test failures with designers to deliver functionally correct design.
• Identify and write functional coverage for stimulus and corner cases.
• Close coverage to plug verification holes and meet tape out requirements.
• Work with the partner IP/SS dv teams to identify and run the ATM and ATE test vectors in SoC environment.
• Write scripts to convert the test vector patterns into format defined by Product Engineering (PE) team.
• Work with the product engineering teams on the delivery of manufacturing test patterns.