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Principal Physical Design Engineer

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We are looking for a highly experienced Electrical or Computer Engineer with extensive background in semiconductor design. You must have excellent communication, collaboration, and teamwork skills, and the ability to contribute to diverse and inclusive teams. In this role, you will be responsible for implementing designs through synthesis, floorplanning, place and route, extraction, timing, and physical verification. This is a fantastic opportunity for someone with a proven track record in semiconductor design to join our team and make a significant impact.

Job description 

Qualifications

Required:

  • BS/MS in Electrical or Computer Engineering
  • 12+ years of experience in semiconductor design.
  • Great communication, collaboration and teamwork skills and ability to contribute to diverse and inclusive teams.
  • Proven track record of implementing designs through synthesis, floorplanning, place and route, extraction, timing, and physical verification.

 

Preferred:

  • Large SoC/CPU/IP design tape-out experience in the latest foundry process nodes.
  • Excellent project management skills and ability to juggle multiple projects at once.
  • Strong understanding of constraints generation, STA, timing optimization, and timing closure.
  • In-depth understanding of design tradeoffs for power, performance, and area.
  • Hands on experience with CTS and global clock distribution methods in multi-voltage, multi-clock, multi-domain, and low power designs.
  • Experience in EDA tools such as Primetime, StarRC, Design Compiler, ICC, Fusion Compiler, Innovus etc.
  • Experience and knowledge of formal equivalency checks, LEC, LP, UPF, reliability, SI, and Noise.
  • Exposure and some hands-on experience with PD flows bring up/setup/flow flush, overall know how of PD-TFM and PD methodology will be a bonus.
  • Strong problem-solving and data analysis skills
  • Automation skills using scripting languages such as Perl, TCL, or Python.
  • Technically leading/guding a eam of multiple PD engineers in order to deliver a Sub-Chip/SoC will be a big plus.

Responsibilities

In this high impact role on the team, you will be responsible to: 

 

  • Demonstrate technical expertise in all aspects of Physical Design, from synthesis to place and route of partitions through all signoff including timing signoff, physical verification, EMIR signoff , Formal Equivalence, and Low Power Verification.
  • Own complete PD execution of Sub-systems/Sub-chips instantiating multiple other Physical partitions.
  • Own partition floorplanning for optimizing blocks for Power, Performance and Area.
  • Have close collaboration with RTL team to help drive and resolve design issues related to block closure.
  • Understand tools, flows, and overall design methodology in design construction, signoff, and optimization with a data driven approach.
  • Implement robust clock distribution solutions using appropriate methods that meet design requirements.
  • Make good independent technical trade-offs between power, area, and timing (PPA).
  • Be able to guide and coordinate with all sub-partitions PD to be able to take the Sub-chip through PD (construction through signoff) closure.
  • Additionally flow flush PD TFM on few design partitions for early identification of any design PD flow issues before every PD TFM release is proliferated and deployed across all partitions/subchips for PD execution.
  • Partner closely with PD flow/CAD team and PD methodology team to flag & fix PD TFM issues upfront and ensure those are fixed in the next PD TFM release from CAD or are updated in the design project layer (as appropriate).


 


 

Set alert for similar jobsPrincipal Physical Design Engineer role in Hyderabad, India or Bengaluru, India
Microsoft Logo

Company

Microsoft

Job Posted

a year ago

Job Type

Full-time

WorkMode

Hybrid

Experience Level

13-17 Years

Category

Engineering

Locations

Hyderabad, Telangana, India

Bengaluru, Karnataka, India

Qualification

Bachelor or Master

Applicants

Be an early applicant

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