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Standard cells Circuit Design Engineer

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We are looking for a candidate with experience in Standard Cell Circuit design. You will be responsible for designing high-performance flip flops, latches, multibit flip flops, voltage level shifters, power optimization cells, and other complex circuits. You should have a strong knowledge of CMOS device characteristics, design rules, Latch Up, and Electromigration. Good understanding of Digital circuits and optimization for better PPA is required. Experience in Statistical/Variation analysis and coding skills in Python/Shell/ICV are preferable. Knowledge of std cell Layout is a plus. The ideal candidate should have 2-4 years of relevant experience along with good verbal and written communication skills.

Job Description and Requirements

Experience in Standard Cell Circuit design of high-performance flip flops, latches, multibit flip flops, voltage level shifters, power optimization cells ,Clock cells other complex circuits.
Strong Knowledge and Hands-on experience in developing environment and extraction of post layout netlist Good understanding of CMOS device characteristics, design rules, Latch Up , Electromigration.
Good understanding of Digital circuits and optimization for better PPA.
Hands on experience in Statistical/Variation analysis
Decent knowledge of Python/Shell/ICV coding will be preferable.
Having Good understanding of std cell Layout is a plus.
Having 2-4 years of relevant experience.
Good verbal and written communication skills.

Set alert for similar jobsStandard cells Circuit Design Engineer role in Bangalore Urban, India
Synopsys Inc Logo

Company

Synopsys Inc

Job Posted

a year ago

Job Type

Full-time

WorkMode

On-site

Experience Level

0-2 Years

Category

Engineering

Locations

Bangalore Urban, Karnataka, India

Qualification

Bachelor

Applicants

Be an early applicant

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Standard cells Circuit Design Engineer

Synopsys Inc

Bengaluru, Karnataka, India

Posted: a year ago

Job Description and Requirements Experience in Standard Cell Circuit design of high-performance flip flops, latches, multibit flip flops, voltage level shifters, power optimization cells ,Clock cells other complex circuits. Strong Knowledge and Hands-on experience in developing environment and extraction of post layout netlist Good understanding of CMOS device characteristics, design rules, Latch Up , Electromigration. Good understanding of Digital circuits and optimization for better PPA. Hands on experience in Statistical/Variation analysis Decent knowledge of Python/Shell/ICV coding will be preferable. Having Good understanding of std cell Layout is a plus. Having 2-4 years of relevant experience. Good verbal and written communication skills.