JOB DESCRIPTION

How You Will Contribute:

Reporting to Sr. Manager ASIC Engineering, as a Senior ASIC Design Engineer, you will define block level design document such as interface protocol, block diagram, transaction flow, pipeline, etc.

You will perform RTL coding, function/performance simulation debug and Lint/CDC/FV/UPF checks.

You will participate in synthesis, timing/power closure and FPGA/silicon bring-up.

You will partake in test plan and coverage analysis of the block and SOC-level verification.

What Does Ciena Expect of You:

Sense of urgency and accountability – what’s important to the customer is important to you; you make getting things done a priority.

Diligence – you will deliver on objectives through meticulous, thorough, and comprehensive work.

Agility – with an ability to flex between the strategic and tactical, you manage competing and ever-changing priorities and maintain a balanced and methodical approach to problem solving.

Communication expertise – you possess the ability to tailor your message and ideas to the audience to ensure understanding and consensus.

Problem solver – you possess the ability to analyze and methodically solve complex technical problems using engineering principles and approaches.

Commitment to learning – you keep abreast of technology developments and are keen to share your knowledge with others.

The Must Haves:

Bachelor / Master or PhD degree in Electrical Engineering coupled with proven experience in ASIC development with Verilog.

Experience with ASIC design verification, synthesis, timing/power analysis and DFT.

At least 10 to 15 years of work experience is required in ASIC Design / Verification or FPGA Design / Verification.

Strong debug and lab experience.

Assets:

Knowledge of high-performance and low-power design techniques.

Knowledge of FPGA and emulation platforms. Knowledge of SOC architecture.

Experience with modern SoC design architectures, ARM/MiPs type processor cores, Ethernet, Networking, and Data Communications.

Knowledge of assertion-based formal verification.

Proficient with a scripting language like Perl.

*California Salary Range : $ 147,800 - $ 236,200

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