Sr Design Engineering Manager (Layout Design)
You will lead custom layout design efforts for DDR IO development, work on physical verifications, and mentor a small team towards a successful IP delivery in Noida, Uttar Pradesh, India. This full-time on-site role requires 3-7 years of experience, with a focus on analog IP like Opamps, Dataconverters, and LDO, knowledge of layout effects on circuits, and experience in DSM technology methodology and scripting.
Job Summary:
Drives development of products and technologies and has material responsibility for the success of that product/technology.
Job responsibilities:
Custom layout design for DDR IO development - Understand design requirements and work closely with the design team and successfully deliver Analog layouts.
- Perform physical verifications like DRC/LVS/Reliability and fixing violations
- Lead custom layout efforts for DDR IO development - Understand design requirements and work closely with the design team and successfully deliver Analog layouts.
- Would be required to lead/mentor a small team of engineers towards a successful IP delivery.
- Perform physical verifications like DRC/LVS/Reliability and fixing violations
Experience and Technical Skills required
Hands on layout design experience in various analog IP like Opamps, Bandgaps, Dataconverters, LDO and PLL etc.
- Understanding layout effects on the circuit such as speed, capacitance, power and area etc., Knowledge of various analog layout techniques like matching, shielding etc.,
- Good understanding of DSM technology methodology, issues etc.,
- Having worked on latest technology nodes, 28nm and below, is desired.
- Must have good communication skills and should be team player.
- Scripting and automation experience is a plus.
- Hands on layout experience in various analog IP like High speed Analog (Serdes), Data converters, power management and PLL etc.
- Understanding layout effects on the circuit such as speed, capacitance, power and area etc.,
- Knowledge of various analog layout techniques, floorplan constraints and IP integration at chip level scenario.
- Good understanding of DSM technology methodology, issues etc.,
- Having worked on latest technology nodes, 28nm and below, is desired.
- Must have good communication skills and should be team player.
- Scripting and automation experience is a plus.
- Good communication skills, documentation and presentation skills.
- Strong analytical and problem-solving skills.
Education Level: Bachelor's Degree / Master’s Degree (MSEE Preferred)
