Responsibilities:

• Perform functional verification, root cause design discrepancies, debug pre-silicon full chip designs and help resolve them.
• Develop Test scenarios to increase the functional coverage for all DRAM and Emerging memory architectures and features.
• Participate in development of advanced verification methodology for Emerging memory products.
• Develop and maintain test benches and test vectors using simulation tools and run regressions for coverage analysis and improvements.
• Perform various checks to ensure accurate timing models.

Core Requirements

• Good interpersonal skills and ability to work well in a team.
• Good in Verilog/SV/UVM concepts and verification
• Deep understanding of fundamental digital design concepts and analytical capability in complex gate level circuit designs.
• Well versed with SPICE and/or Verilog simulations and debug.
• Hands-on experience in developing/understanding building block schematics, memory schematics, running circuit simulation with spice simulators, DC analysis, transient analysis.
• Experience in deciphering circuit behavior from schematics.
• Familiarity with circuit characterization, timing libraries - files and formats, timing arcs
• Experience in Verilog MOS switch level models and netlist simulation with zero delay, unit delay, and path delay simulations.
• Debugging Gate level simulation failures and root causing the failures to actual circuits. Accomplish what-if analysis by doing the change and making sure the fix can solve the issue.
• Hands-on knowhow of System Verilog Assertions to specify expected design behavior
• Familiarity with UVM is a plus.
• • Gate level simulation, spice correlation, Debug failures and provide fixes at gate or transistor level - as applicable.

Qualifications & Skills:

• Experience in DRAM, SRAM or other memory related fields.
• Experience in AMS verification and co-sim.
• Good in verification approach, flow and concepts.

Education and Experience:

. Post Graduate Degree in Electronics Engineering or related engineering field requirement.

Experience Range: 7-11 years