Digital Verification Engineer
Seeking a highly motivated and innovative engineer with background in high-speed protocols and the wish to grow on protocol knowledge by verification related work. Working as part of an experienced digital design and verification team. The position offers an excellent opportunity to work with experts on several fields. The candidate will be involved at specify, verification and implement phases of state-of-the-art products.
 
This is an office-based role in Bucharest. We can support with relocation if needed.
We work in a hybrid mode: 2 days from home and 3 days from office.
Our office is located in an attractive areas, close to Piata Romana.

Key responsibilities:

• Identify verification environment requirements from its various sources (Specifications, Design functionality, Interfaces, etc …)
• Generate verification test plan, verification environment documentation and test environment usage documentation
• Define, develop, and verify complex UVM verification environments
• Evaluates and exercises various aspects of the development flow. May include such items as Verilog/SystemVerilog development, functional simulation, constraint development, test planning, behavioural modelling, and verification coverage metrics (functional coverage and code coverage)
• Identify design problems, possible corrective actions and/or inconsistencies on documented functionality

 
Key Qualifications

• Proven desire to learn and explore new state of the art technologies
• Demonstrate good review and problem-solving skills
• Knowledgeable with Verilog, VHDL and/or SystemVerilog
• Knowledgeable with scripting languages (BASH/TCSH/PERL/PYTHON/TCL) is a plus
• Understanding of verification methodology such as UVM is a plus
• Good organization and communication skills
• 3+ years of relevant experience
• Proficient in Romanian and English