Job description 

THE ROLE (ASIC Lead – Director):

• As an Individual Contributor (IC) role you will be driving and leading Large size ASIC from customer NL delivery to Tape-out and product ramp to production covering aspects of IP delivery to customer, DFT implementation on NL, DFX Verification, Physical Design implementation and signoff.
• Single POC (Point of Contact) to customer.  Overall program ownership.
• Work with customer on ASIC program definition, IP requirement, feature alignment, bounding box analysis and drive to optimal solution.
• Work with Design / DFX / DV / PD lead to drive successful ASIC execution.
• Work with internal / external IP team for IP requirement, collaterals, deliverables, and negotiations.
• Working in tight constraints of PPAS for latest technology node..
• Work with product engineering team on test vectors requirement, signoff and Si bring up strategy.
• Work with program management team for ASIC program planning, schedule, resource demand/supply, critical path analysis, dev cost and execution.

THE PERSON:

• Leader with strong self-driving ability and ability to work with urgency.
• Strong debug capability on failure analysis, debug/ triage and solutioning.
• Need excellent communication skills, both written and oral.
• Strong interpersonal and stakeholder management skills to execute under tighter constraints.

KEY RESPONSIBILITIES:

• As an ASIC SOC lead driving multiple ASIC execution from NL to tape-out.
• Contribute to Bounding box analysis, feature alignment, scope change, DFT, Test-plan, Verification, Coverage analysis, Gate Sims, Power Optimization, Floorplan, Convergence and Tape-outs.
• Running regular execution meetings, scrums, standing meetings and resolving bottlenecks.
• Representing SOC team execution / progress to customer regular basis.
• Managing scope change, bug board, late bug fixes, ECO analysis and approvals.
• Project planning, schedule, deliverables, risk/ mitigations. Presenting status update to senior executives.

PREFERRED EXPERIENCE:

• Experience of successfully leading minimum 2 ASIC end-to-end execution as an overall ASIC lead and having experience in directly managing customer interface.
• Experience in one or more networking ASIC is preferred.
• Handson experience on Arch, IP Design, DFX, Physical Design implementation is a must.
• Experience in ASIC execution, customer engagement, deliverables.
• Comfortable with design/implementation tools and flows like VCS, SOC Connectivity, Spyglass Lint/CDC/RDC, VCLP, Synthesis DC/FC, ICC, and Physical design implementation/signoff tools.
• Expertise in ECO analysis and PD aware ECO implementation aspects.
• Strong knowledge on Gate level simulation challenges, debug, and root cause.
• Expertise in SOC architecture, System bus and IO protocol understanding (e.g. AXI, CHI, PCIe, DDR etc.)
• Good understanding of System integration, multi-die methodology, packaging, yield, and system solution.
• Expertise in project planning, IP delivery timelines, deliverables and quality checks, Resource planning, critical path analysis, risks, and mitigation plan.
• Comfort with Scripting such as Perl, shell, Python and TCL is a plus.
• Immediate joiner is preferred.

ACADEMIC CREDENTIALS:

• ~20+ years of strong experience in leading end to end ASIC execution.
• BE/B.Tech/ME/MTECH/MS or equivalent ECE/EEE

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