Job description 

About Juniper SLICON Group:

At Juniper Silicon Group, we push the boundaries of what is possible in a piece of silicon die. We build cutting-edge networking chips used to build world-class routers and switches.  

Bring your passion and there are no boundaries to what you can accomplish here. We are like a start-up in a big company. Year after year, our group builds the most powerful and highest-density networking chips.  If you are ready to innovate and solve the most complex networking/AI/ML problems, then the Juniper silicon team is right for you. We build careers and ensure everyone grows to their full potential. 

We are working on the latest technologies:

• 3 nm
• 50-1000 million placeable objects
• 500-1000 million gates
• 3-100B transistors
• 288 high-speed links (224G)
• Clock frequency – 1000- 1670 MHz

About the Position:

• ASIC Frontend verification engineer adept at System Verilog, UVM, C-modelling, and industry-standard simulation tools

Responsibilities:

• Create a verification plan for testing ASIC/FPGA designs
• Create a verification environment in System Verilog and UVM
• Create, run, and debug tests in System Verilog/UVM environment

Qualification:

• Bachelor’s degree required (Master’s strongly desired) in Electrical Engineering or Computer Science/Engineering with 3 to 6 years' experience. 
• Strong analytical/problem-solving skills.
• Experience in constrained-random verification with methodologies such as UVM is required – Should have developed block level/full-chip test benches from scratch using system Verilog/UVM in prior work. 
• Experience using emulation systems is a plus. 
• Knowledge of Computer Architecture/networking protocols and machine learning through previous work is a plus but not required. 
• Knowledge of Perl/Python/C/C++.  
• Excellent written and verbal communication skills are necessary. 

#JuniperASICEngineeringIndia