What you'll be doing:

• Architect, design, and integrate system level clock management policies and features to optimize product performance, power, and stability for different markets and use cases.
• Develop innovative system features to address low power, low noise, perf/watt efficient product requirements; prototype features on existing silicon; analyze costs vs benefits; build and maintain feature bring-up plans for new silicon and participate in bring-up execution.
• Keep track of the latest industry direction, market needs, and technology development, and incorporate them into future roadmaps to build more competitive products.
• Work closely and proactively with other engineering teams such as system architecture, ASIC/PCB design, software/firmware, HW/SW QA and Applications Engineering to drive design, development, debug and release of next generations products.
• Lead debugging, craft WARs, and support manufacturing and customer issues on relevant features.

What we need to see:

• BS or MS degree in EE/CE or equivalent experience.
• 10+ years of proven experience in silicon design, validation, power analysis, and debug.
• Strong EE fundamentals, knowledgeable in clock design, digital design, low power design, DVFS, signal integrity, statistics, timing analysis, sampling, architecture, filters, and scripting.
• Strong understanding of firmware/driver structures and their interaction with HW.
• Validated hands-on lab experience with silicon bringup, lab debug and lab tools (oscilloscopes, multimeters, logic analyzers).
• Helpful to have prior experience with clocks, PLL, and VCO design, characterization, validation, bringup, and debug.
• Excellent problem solving, teamwork, and interpersonal skills.
• Experience with Python, Perl, C/C++, Windows, and Linux is a plus.