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Senior System Clocks Management Engineer

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We are looking for an experienced EE/CE professional to architect, design, and integrate system level clock management policies and features. You will be responsible for optimizing product performance, power, and stability for different markets and use cases. Additionally, you will develop innovative system features to address low power and low noise requirements, and collaborate with other engineering teams to drive the development of next generation products. Join us if you have a strong background in silicon design, validation, and power analysis.

What you'll be doing:

  • Architect, design, and integrate system level clock management policies and features to optimize product performance, power, and stability for different markets and use cases.
  • Develop innovative system features to address low power, low noise, perf/watt efficient product requirements; prototype features on existing silicon; analyze costs vs benefits; build and maintain feature bring-up plans for new silicon and participate in bring-up execution.
  • Keep track of the latest industry direction, market needs, and technology development, and incorporate them into future roadmaps to build more competitive products.
  • Work closely and proactively with other engineering teams such as system architecture, ASIC/PCB design, software/firmware, HW/SW QA and Applications Engineering to drive design, development, debug and release of next generations products.
  • Lead debugging, craft WARs, and support manufacturing and customer issues on relevant features.

 

What we need to see:

  • BS or MS degree in EE/CE or equivalent experience.
  • 10+ years of proven experience in silicon design, validation, power analysis, and debug.
  • Strong EE fundamentals, knowledgeable in clock design, digital design, low power design, DVFS, signal integrity, statistics, timing analysis, sampling, architecture, filters, and scripting.
  • Strong understanding of firmware/driver structures and their interaction with HW.
  • Validated hands-on lab experience with silicon bringup, lab debug and lab tools (oscilloscopes, multimeters, logic analyzers).
  • Helpful to have prior experience with clocks, PLL, and VCO design, characterization, validation, bringup, and debug.
  • Excellent problem solving, teamwork, and interpersonal skills.
  • Experience with Python, Perl, C/C++, Windows, and Linux is a plus.


 

Set alert for similar jobsSenior System Clocks Management Engineer role in Santa Clara, United States
NVIDIA Logo

Company

NVIDIA

Job Posted

a year ago

Job Type

Full-time

WorkMode

On-site

Experience Level

8-12 Years

Category

Engineering

Locations

Santa Clara, California, United States

Qualification

Bachelor

Applicants

Be an early applicant

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