Job Responsibilities

• Review SerDes standards to develop analog top and sub-block specifications.
• Ability to lead projects and guide junior engineers.
• Exercise independent judgement to identify and refine circuit architectures to achieve optimal power, area and performance targets.
• Propose design and verification strategies that efficiently use simulator features to ensure highest quality design.
• Oversee physical layout to minimize the effect of parasitics, device stress, and process variation.
• Review and present simulation data for peer and customer review.
• Define and document design features and test plans.
• Propose solutions for post-silicon design updates.

Qualifications

• Bachelor's degree in Electrical Engineering, Computer Engineering, or similar technical field
• BSEE degree and 12-15 years of experience in IC design, or MSEE (or PhD) with 8-12 years of experience.
• Design experience in high speed PHY such as DDR, HBM or SERDES
• In depth familiarity with transistor level circuit design - sound CMOS design fundamentals.
• Detailed design experience with one, and familiarity with several other SerDes sub-circuits: receive equalizers, samplers, voltage/current-mode drivers, serializers, deserializers, voltage-controlled oscillator, phase mixer, delay-locked loop, phase locked loop, bandgap reference, ADC, DAC.
• Familiarity with custom digital design (i.e. high-speed critical paths).
• Understanding of design for reliability (i.e. EM, IR, aging, etc.)
• Understanding of layout effects (i.e. matching, reliability, proximity effects, etc.).
• Experience with tools for schematic entry, physical layout, and design verification.
• Understanding of SPICE simulators and simulation methods.
• Knowledgeable in Verilog-A for analog behavioral modeling and simulation-control/data-capture.
• Experience with TCL, Perl, C, Python, MATLAB, or other scripting languages is desired.
• Hands-on experience with physical layout of high-speed circuits is a plus.
• Good communication and documentation skills