The Job logo

What

Where

IP Verification Lead

ApplyJoin for More Updates

You must Sign In before continuing to the company website to apply.

THE ROLE:

The Core design and verification team is responsible for development of ‘High performance and Ultralow power x86 microprocessor core’. The role provides a unique opportunity to work at the micro-architectural level of the next-gen Core, with exposure to designs that defines the next wave of client (laptops/ultra-books/think-clients) and custom designs. The multi-billion gate complexity and high-frequency (GHz) design development gives the learning experience of the latest and greatest design and verification methodologies, using cutting edge advanced technology nodes.

 

 

THE PERSON:

Candidates should have solid track record of working on complex designs with hands on experience on architecting and developing test-bench, test-bench components, test-planning and execution of testplan, coverage development and closure. Candidate should have working experience with global teams spread across different geography and time-zones.

 

KEY RESPONSIBILITIES:

  • ASIC design verification experience 12+ years
  • Verification of high performance x86-core ISA features
  • Architecting and development of testbench, test-bench components for high performance Cache, x86 ISA features, clock/reset/power features of processor.
  • Development of detailed test plans and driving the execution of test plan, including functional coverage.
  • Understanding the existing test bench setup and look for opportunities to improve the existing test bench.
  • Adhering to coding guideline practices, develop and implement code review process.
  • Collaborate with global design verification teams and drive effectively the execution of the verification plans.
  • Your commitment to innovating as a team demonstrated through excellent communication, knowledge of proper documentation techniques, and independently driving tasks to completion.

 

PREFERRED EXPERIENCE:

  • Strong understanding the design and verification life cycle.
  • Hands on verification experience with C/C++/SystemVerilog testbench development.
  • Hands on experience with coverage planning, coding and coverage closure.
  • Experience with x86, ARM or any other industry standard microprocessor ISA.
  • Experience with Cache, Coherency and Data-Consistency verification.
  • Experience in clocking, reset, power-up sequences and power management verification.
  • Understanding of low power design verification techniques is a plus.
  • Lead verification team from all aspects of the deliverables.
  • Mentor the junior members of the verification team to meet the team goals
  • Represents AMD to the outside technical community, partners and vendors
  • Collaborate with SOC team, multi-geographical design teams for alignment of features/scoping/problem-solving.
  • Highly motivated to seek out solutions and willing to learn new skills to fulfill job requirements;
  • Proven interpersonal skills, leadership and teamwork;
  • Excellent writing skills in the English language, and good organizational skills required;
  • Skilled at prioritization and multi-tasking;
  • Good understanding of engineering terminology used within the semiconductor industry;
  • Good understanding of digital design concepts;
  • Knowledge of, or experience in, functional design/RTL and physical design flow is highly desired.

 

ACADEMIC CREDENTIALS:

  • Master’s degree preferred with emphasis in Electrical/Electronics Engineering, Computer Engineering, or Computer Science with a focus on computer architecture
Set alert for similar jobsIP Verification Lead role in Hyderabad, India
AMD Logo

Company

AMD

Job Posted

a year ago

Job Type

Full-time

WorkMode

On-site

Experience Level

13-17 years

Category

Software Engineering

Locations

Hyderabad, Telangana, India

Qualification

Master

Applicants

Be an early applicant

Related Jobs

AMD Logo

CPU/IP Design Verification Engineer

AMD

Bengaluru, Karnataka, India

Posted: 9 months ago

Seeking a CPU/IP Design Verification Engineer to join the Radeon Technologies Group in Bengaluru, Karnataka, India. You will be responsible for leading the Core Power Management Team, developing test plans, coding in asm, c++, and maintaining UVM test bench components. The ideal candidate should have experience in IP level verification, UVM, SV, C++, and possess strong digital design concepts.

Qualcomm Logo

Camera IP Design Verification - Sr Engineer

Qualcomm

Hyderabad, Telangana, India

Posted: a year ago

Job Area: Engineering Group, Engineering Group > Hardware Engineering   General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements.   Minimum Qualifications: • Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience.   For the role of camera verification engineer, candidate will be responsible for IP Level Verification of Qualcomm Spectra Camera Sub Systems Modules for next gen Qualcomm product portfolio. This role will require the candidate to understand details of the camera signal processing modules, verify them at module & subsystem level for enhanced features. Engineer should be able to own the verification of IP level modules end to end with continuous enhancements. ​ 8+ years of experience in RTL design verification using SystemVerilog/UVM and industry-standard simulation tools (Mandatory) Experience on camera verification is a big plus    Expertise in  coverage closure , RTL debug skills Expertize in SV – UVM, Assertions based verification, DPI Familiarity with bus protocols like AHB, AXI, ARM based system architecture Experience with Perl, Python, or similar scripting language Excellent problem solving skills

AMD Logo

IP Verification Lead Engineer

AMD

Bengaluru, Karnataka, India

+1 more

Posted: a year ago

WHAT YOU DO AT AMD CHANGES EVERYTHING We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences – the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world’s most important challenges. We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives.  AMD together we advance_   MTS SILICON DESIGN ENGINEER       THE ROLE:   The focus of this role is to plan, build, and execute the verification of new and existing features for AMD’s graphics processor IP, resulting in no bugs in the final design.       THE PERSON:    You have a passion for modern, complex processor architecture, digital design, and verification in general. You are a team player who has excellent communication skills and experience collaborating with other engineers located in different sites/timezones. You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems.     KEY RESPONSIBILITIES:    Collaborate with architects, hardware engineers, and firmware engineers to understand the new features to be verified  Build test plan documentation, accounting for interactions with other features, the hardware, the firmware, and the software driver use cases  Estimate the time required to write the new feature tests and any required changes to the test environment  Build the directed and random verification tests  Debug test failures to determine the root cause; work with RTL and firmware engineers to resolve design defects and correct any test issues   Review functional and code coverage metrics – modify or add tests or constrain random tests to meet the coverage requirements     PREFERRED EXPERIENCE:    Proficient in IP level ASIC verification  Proficient in debugging firmware and RTL code using simulation tools   Proficient in using UVM testbenches and working in Linux and Windows environments  Experienced with Verilog, System Verilog, C, and C++    Graphics pipeline knowledge  Developing UVM based verification frameworks and testbenches, processes and flows  Automating workflows in a distributed compute environment.    Exposure to simulation profile, efficiency improvement, acceleration, HLS tools/process  Strong background in the C++ language, preferably on Linux with exposure to Windows platform  Good understanding and hands-on experience in the UVM concepts and SystemVeriloglanguage  Good working knowledge of SystemC and TLM with some related experience.    Scripting language experience: Perl, Ruby, Makefile, shell preferred.    Exposure to leadership or mentorship is an asset  Desirable assets with prior exposure to video codec system or other multimedia solutions.