What you'll be doing:

Build a Full-Chip floor plan layout design from early assembly/planning through implementation and signoff.

Work closely with partition owners and Full Chip STA engineers to assure high quality and timely convergence.

Involved in defining and implementing efficient and high-quality Full Chip physical design tools, flows, and methodologies.

As a part of your role, you will gain hands-on experience in implementing unit/partition level BE design (RTL2GDS).

What we need to see:

B.S. in Electrical Engineering or Electrical Practical Engineer certificate, or equivalent experience. 

At least 5 years of relevant experience. 

Proven experience in P&R and Layout tools, TCL scripting, expertise in Netlist-to-GDSII flow is an advantage.

Great teammate, responsible and motivated.

Experience in unit and top-level floor planning, full-chip clock tree, power grid planning, 7nm DRC/LVS.