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Senior Physical Design Engineer, Full-Chip Layout

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What you'll be doing:

Build a Full-Chip floor plan layout design from early assembly/planning through implementation and signoff.

Work closely with partition owners and Full Chip STA engineers to assure high quality and timely convergence.

Involved in defining and implementing efficient and high-quality Full Chip physical design tools, flows, and methodologies.

As a part of your role, you will gain hands-on experience in implementing unit/partition level BE design (RTL2GDS).

 

What we need to see:

B.S. in Electrical Engineering or Electrical Practical Engineer certificate, or equivalent experience. 

At least 5 years of relevant experience. 

Proven experience in P&R and Layout tools, TCL scripting, expertise in Netlist-to-GDSII flow is an advantage.

Great teammate, responsible and motivated.

Experience in unit and top-level floor planning, full-chip clock tree, power grid planning, 7nm DRC/LVS.

Set alert for similar jobsSenior Physical Design Engineer, Full-Chip Layout role in Tel Aviv, Israel
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Company

NVIDIA

Job Posted

a year ago

Job Type

Full-time

WorkMode

On-site

Experience Level

3-7 years

Locations

Tel Aviv, Tel Aviv District, Israel

Qualification

Bachelor

Applicants

Be an early applicant

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Full Chip STA Engineer

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Tel Aviv, Tel Aviv District, Israel

Posted: a year ago

What you will be doing: Be in charge of full chip level STA convergence from early stages to signoff. Take part in Full Chip floor plan design and Netlist creation with aim to optimize timing convergence and work efficiency. Define and optimize, together with CAD, STA signoff flows and methodologies. Digital Partitions' and analog IPs' timing integration, giving feedback and driving convergence. Work closely with logic design and DFT engineers to define and implement constraints for the various work modes, including optimizing them for runtime and efficiency.   What we need to see: B.SC./ M.SC. in Electrical Engineering/Computer Engineering. 3+ years of experience in physical design and STA Proven experience in RTL2GDS and STA flows and methodologies. Familiarity with physical design EDA tools (such as Synopsys, Cadence, etc.) and timing signoff (Primetime). Great teammate.