As a DFT engineer Direct Responsibilities of the role, but not limited to, working on various aspects of IP and SoC DFT including Spyglass DFT, RTL implementation, Verification, Scan, and ATPG. The candidate must be able to drive the DFT implementation for various features incl Scan, MBIST, TAP, etc. Exposure to full SoC end to end. Previous experience working with manufacturing engineering, pattern delivery, and post-silicon support is a definite plus.
Education MS or BS Degree in technical discipline.
The mission of the Emerging Growth and Incubation (EGI) group is to create an environment to identify, incubate and scale new billion-dollar businesses leveraging Intel's competitive advantages. EGI is a fast paced, dynamic and startup-like organization that is responsible for incubating new ideas within Intel. We have over 1500 employees globally. Our portfolio includes HW, SW, Solutions and SaaS businesses.
All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.
We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits here: https://www.intel.com/content/www/us/en/jobs/benefits.html
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This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site.In certain circumstances the work model may change to accommodate business needs.