Senior RTL Design Engineer

Technology, Data & Digital · Software & Web Development · Embedded Systems

Smart Summary

AI-generated overview of this position

HCLTech is seeking a Senior RTL Design Engineer with 2-5 years of experience in RTL coding using Verilog/SV and design with Xilinx or Altera devices. The role involves supporting lab debug, understanding FPGA debugging techniques, and experience with CDC/Linting/Tool Flow. Responsibilities include collaborating with stakeholders, developing designs, mentoring junior designers, and integrating with cross-functional teams.

Job Summary

Candidates with 2 to 4 years experience is mandatory

Experience in RTL coding using Verilog/SV

Experience in design using Xilinx or Altera devices

Experience in using Vivado or Quartus

Experience in supporting lab debug

Good understanding of FPGA debugging techniques

2 to 5 years experience in front end design

Experi

Candidates with 2 to 4 years experience is mandatory

Experience in RTL coding using Verilog/SV

Experience in design using Xilinx or Altera devices

Experience in using Vivado or Quartus

Experience in supporting lab debug

Good understanding of FPGA debugging techniques

2 to 5 years experience in front end design

Experience in CDC/Linting/Tool Flow

Experience with ASIC/SoC development flow including synthesis/Timing Constraints development is preferred

Experience in RTL Synthesis

Scripting experience is preferable

ence in CDC/Linting/Tool Flow

Experience with ASIC/SoC development flow including synthesis/Timing Constraints development is preferred

Experience in RTL Synthesis

Scripting experience is preferable

Key Responsibilities

1. Collaborate With Stakeholders To Gather And Refine Rtl Design Requirements, Ensuring Clear Understanding And Alignment With Project Goals.
2. Develop And Implement Prototypes And Proof-Of-Concept Designs Using Vhdl/Verilog, Validating Design Decisions Against Project Specifications.
3. Mentor And Guide Junior Designers By Sharing Knowledge And Expertise Through Structured Training Sessions And Comprehensive Documentation.
4. Work Closely With Cross-Functional Teams To Ensure That Rtl Design Integrates Seamlessly With Overall Project Architectures And Goals.
5. Partner With Quality Assurance Teams To Define Testing Plans And Methodologies, Ensuring The Delivery Of High-Quality Rtl Designs That Meet Industry Standards.

Skill Requirements

1. Strong Understanding Of Rtl Design Principles And Methodologies.
2. Proficient In Vhdl/Verilog For Digital Design And Simulation.
3. Familiarity With Fpga And Asic Design Flows And Tools.
4. Good Communication Skills To Interact Effectively With Stakeholders And Team Members.

Other Requirements

1. Optional But Valuable: Certification In Rtl Design Or Equivalent Recognized Qualification.
2. Optional But Valuable: Completion Of Relevant Training Courses In Digital Design And Verification Methodologies.

#RTL Design#Verilog#FPGA#ASIC#Bangalore#Senior Engineer#HCLTech
HCLTech Logo

Company

HCLTech

Job Posted

1 week ago

Employment Type

Full Time

WorkMode

On Site

Experience Level

Senior

Locations

Bangalore, India

Applicants

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